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CL-GD6205 Schematic ( PDF Datasheet ) - Cirrus Logic

Teilenummer CL-GD6205
Beschreibung Single DRAM LCD/VGA Controllers
Hersteller Cirrus Logic
Logo Cirrus Logic Logo 




Gesamt 30 Seiten
CL-GD6205 Datasheet, Funktion
CL-GD62XXwww.DataSheet4U.com
® Preliminary Data Book
FEATURES
s IBM®_VGA hardware-compatible
s Integrated RAMDAC
s Integrated programmable frequency synthesizer
— 65 MHz at 5.0V; 40 MHz at 3.3V
s Supports single 256K x 16 DRAM configuration
— Symmetric or asymmetric RAS/CAS-address DRAM
s Color STN panel support (CL-GD6225/’6235 only)
— Dual-scan color STN panel support (CL-GD6235 only)
— 8- and 16-bit interfaces (no extra components required)
— Up to 256 simultaneous colors from a palette of 256K
s Integrates color TFT panel support
— Supports 9-, 12-, 15-, and 18-bit TFT panels
— Up to 256 simultaneous colors from a palette of 256K
s Connects directly to local bus, ISA bus (PC AT) or PI
bus (CL-GD6205 connects to ISA bus only)
s Windows performance-improvement features
— True packed-pixel addressing
— Improved data latches for block moves
— Color expansion for 8 bits-per-pixel graphics
— 32 x 32 hardware cursor (2 bits-per-pixel)
s Supports 3.3V and 5.0V mixed-voltage operation
s Standby and Suspend modes save power
— Internal timers for backlight control and Standby mode
— Dedicated Hardware-suspend Mode pin
— 32-kHz DRAM refresh clock in Suspend mode
s Frame-Accelerator for low-active power
— No additional DRAMs required
— Supports self-refresh DRAMs
s Simultaneous CRT and LCD (SimulSCAN) operation
(cont.)
Single DRAM LCD/VGA
Controllers for Monochrome/
Color Notebook Computers
OVERVIEW
The CL-GD62XX (CL-GD6205/’6215/’6225/’6235) fam-
ily of advanced single-chip flat panel VGA controllers are
designed for use in portable systems with stringent
power consumption and form-factor requirements.
Product family pin compatibility provides easy upgrade
capability to color or higher-performance systems.
Integration of the frequency synthesizer, RAMDAC,
monochrome and color STN/TFT panel interfaces mini-
mizes the form-factor requirement for color and mono-
chrome graphics subsystems. All necessary panel-
power sequencing logic has been integrated into the
CL-GD62XX family, and a complete graphics subsystem
can be built using only two active components (in less
than three square inches).
The CL-GD62XX family uses a single 256K x 16 DRAM
(or four 256K x 4 DRAMs) for video memory. For added
flexibility, dual-CAS*-DRAM and dual-WE*-DRAM con-
figurations are supported.
With integrated Frame-Accelerator technology, the
CL-GD62XX controllers feature low-power LCD opera-
tion, yet support high LCD panel vertical-refresh rates.
No additional DRAMs are required for frame
(cont.)
Functional
Block Diagram
3.3V
3.3V or 5V
256K x 16
DRAM
3.3V or 5V
CL-GD62XX
160-Pin PQFP
3.3V
or
5V
3.3V
or
5V
5
4
3
2
1
0
ANALOG CRT
5
4
3
2
1
0
REFERENCE FREQUENCY
MONOCHROME OR
COLOR LCD PANEL
October 1993
Thi d
d ihF M k 404






CL-GD6205 Datasheet, Funktion
CL-GD62XXwww.DataSheet4U.com
LCD VGA Controller Family
Revision History
Major changes between the previous version, dated September 1992, and this version are listed below.
General
The major addition to this data book is information specific to the CL-GD6235 device.These additions are
labeled as CL-GD6235 only', if they do not apply to other devices in the family. Also, the LCD Timing
(Shadow) registers (Rxx), that were listed with the CR1D[7] register description, have been broken out
into individual register descriptions at the end of Section 6.0.
Specific
Section Revision
1.0 The CL-GD6235 is added to the CL-GD6225 pin diagram. One of the filter capacitors in the AVDD fil-
ter circuit has been changed from '.1't9'1.0' CLF. The Pin Summary Tables for the Host Interfaces
has been consolidated into one table. The Output Loading Parameters have been moved from the
Pin Summary tables to the Electrical Test section.
2.0 The detailed pin descriptions have been modified for consistency and to add the pin numbers to the
individual pins. Information has been added to many of the descriptions.
2.4 The recommended filter circuit components have been changed.
2.5 The IREF circuit for 3.3V operation has been added.
3.0 The functional description has been modified to add CL-GD6235-specific information.
3.8 Standby and Suspend mode descriptions have been modified for clarity. Also, the power sequencing
parameters have been changed.
4.3 The Host Interface Signals table has been included in Section 1.9, Pin Summary.
6.0 The register information has been expanded to include CL-GD6235–specific register data. Register
descriptions have been added for:
CR29 — Configuration register
ROX through REX — LCD Timing registers (these3hadow' registers were described under the
CR1D[7] register description).
7.2 DC Specifications — the CMOS input-threshold and output-limit specifications have been corrected.
An Output Loading table has been added.
7.6 AC Specifications — many of the tables and waveforms have consolidated to reflect operating rela-
tionships, and some new parameters have been added to the Memory Read and Write tables. Most
of the limits are equal to or tighter than the original data. The STN and TFT panel interface timing
specifications have been modified to reflect more current LCD-industry limits.
8.0 Package dimensions have been modified slightly to reflect the latest plastic package.
6 October 1993
PRELIMINARY DATA BOOK

6 Page









CL-GD6205 pdf, datenblatt
CL-GD62XXwww.DataSheet4U.com
LCD VGA Controller Family
1.6 TFT Color Panel Connections — ’386SX Local Bus Using 256K x 16 DRAM with
Dual WE*
BVDD
CVDD
’386SX Local Bus Interface
SW3 (Option)
SW3
SW2 (Option)
SW2
SW1 (Option)
SW1
AVDD1
33
RESET
CPU-RESET
CLK2
W/R#
M/IO#
ADS#
A[16:2]
A1
BLE#
pull-up
READY#
INTR
A[23:17]
D[15:0]
BHE#
(Note a)
(Note a)
LBA#
OSC
32KHz
No Connect
(Note b)
RESET
AEN
IOWR*
IORD*
SMEMW*
SMEMR*
BALE
SA[16:2]
SA1
SA0
REF*
IOCHRDY
IRQ
LA[23:17]
SD[15:0]
SBHE*
MEMCS16*
IOCS16*
OSC
32KHz
EROM*
CLK1X
AVDD4
33
DVDD
2.2 µF
75
1.0 µF
2.2 µF
75
1.0 µF
AVDD1
AVSS1
VFILTER
AVDD4
AVSS4
MFILTER
D[15:8]
UWE*
D[7:0]
LWE*
A9
DUAL-
A8
WE* A[7:1]
DRAM
A0
256K x 16
RAS*
CAS*
OE*
MA[0]
MA[7:1]
MA[8]
WE1*
WE0*
MA[8:0]
RAS*
CAS*
OE*
DVDD1
DVDD2
MD[15:8]
WE1*
MD[7:0]
WE0*
MA9
MA[8:0]
RAS*
CAS*
OE*
VSS[11:1]
AVDD
BVDD
AVDD2
AVDD3
RED
GREEN
BLUE
IREF
AVSS3
AVSS2
HSYNC
VSYNC
PVDD1
IREF
PVDD
RED
GREEN
BLUE
150 HSYNC
VSYNC
Video Connector
DE
UD[3:0]
FPVDCLK
Typical TFT Color Panel
DCLK
Power
LLCLK
HSYNC
LFS VSYNC
MOD
DTMG
LD[3:0]
R[5:0] (Note c)
R[5:0]
G[5:0] (Note c)
G[5:0]
B[5:0] (Note c)
B[5:0]
ACTi
ACTi (Option)
R[5:0]
G[5:0]
B[5:0]
Keyboard Interrupt
SUSPEND
STANDBY
Suspend (Closed Cover)
Panel Standby
DC Power Module
FPVEE BIAS PWR On BPO
PWR_BIAS
FPVCC Panel Drive On
FPBACK Backlight On
NPD (Option)
NPD
PDO
BLO
PWR_LOGIC
PWR_INVERTER
LCD_RSET*
AC POWER
VEE
VLP
VBL
LCD_RSET*
NPD
LCD-Reset* (Option)
LCDRSET*
DUALCAS
BUSCONF*
Local Bus (Note a)
TWR*
IntCLK*
No Connect
NOTES:
a. Refer to Table 2-1 for bus configuration.
b. Ground these input signals when not used.
c. See Panel Interface Connection Tables for specific pin connections.
16
PIN INFORMATION
October 1993
PRELIMINARY DATA BOOK

12 Page





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