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8583T Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer 8583T
Beschreibung PCF8583T
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 28 Seiten
8583T Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
www.DataSheet4U.com
PCF8583
Clock/calendar with 240 × 8-bit
RAM
Product specification
Supersedes data of 1997 Mar 28
File under Integrated Circuits, IC12
1997 Jul 15






8583T Datasheet, Funktion
Philips Semiconductors
Clock/calendar with 240 × 8-bit RAM
www.DataSheet4U.com
Product specification
PCF8583
handbook, full pagewidth
MSB
LSB
7
6
5 43
2
1
0
memory location 00
reset state: 0000 0000
MRB017
timer flag (50% duty factor
seconds flag if alarm
enable bit is 0)
alarm flag (50% duty factor
minutes flag if alarm
enable bit is 0)
alarm enable bit:
0 alarm disabled: flags toggle
alarm control register disabled
(memory locations 08 to 0F
are free RAM space)
1 enable alarm control register
(memory location 08 is the
alarm control register)
mask flag:
0 read locations 05 to 06
unmasked
1 read date and month count
directly
function mode :
00 clock mode 32.768 kHz
01 clock mode 50 Hz
10 event-counter mode
11 test modes
hold last count flag :
0 count
1 store and hold last count in
capture latches
stop counting flag :
0 count pulses
1 stop counting, reset divider
Fig.3 Control/status register.
1997 Jul 15
6

6 Page









8583T pdf, datenblatt
Philips Semiconductors
Clock/calendar with 240 × 8-bit RAM
www.DataSheet4U.com
Product specification
PCF8583
handbook, full pagewidth
MSB
7 654
MRB007
LSB
321 0
memory location 08
reset state: 0000 0000
timer function :
000 no timer
001 units
010 100
011 10 000
100 1 000 000
101 not allowed
110 not allowed
111 test mode, all counters
in parallel
timer interrupt enable :
0 timer flag, no interrupt
1 timer flag, interrupt
clock alarm function :
00 no event alarm
01 event alarm
10 not allowed
11 not allowed
timer alarm enable :
0 no timer alarm
1 timer alarm
alarm interrupt enable :
0 alarm flag, no interrupt
1 alarm flag, interrupt
Fig.10 Alarm control register, event-counter mode.
In the clock mode, if the alarm enable is not activated
(alarm enable bit of control/status register is logic 0), the
interrupt output toggles at 1 Hz with a 50% duty cycle (may
be used for calibration). This is the default power-on state
of the device. The OFF voltage of the interrupt output may
exceed the supply voltage, up to a maximum of 6.0 V.
A logic diagram of the interrupt output is shown in Fig.11.
7.10 Oscillator and divider
A 32.768 kHz quartz crystal has to be connected to OSCI
(pin 1) and OSCO (pin 2). A trimmer capacitor between
OSCI and VDD is used for tuning the oscillator (see quartz
frequency adjustment). A 100 Hz clock signal is derived
from the quartz oscillator for the clock counters.
In the 50 Hz clock mode or event-counter mode the
oscillator is disabled and the oscillator input is switched to
a high impedance state.
This allows the user to feed the 50 Hz reference frequency
or an external high speed event signal into the input OSCI.
7.11 Initialization
When power-up occurs the I2C-bus interface, the
control/status register and all clock counters are reset.
The device starts time-keeping in the 32.768 kHz clock
mode with the 24 h format on the first of January at
0.00.00: 00. A 1 Hz square wave with 50% duty cycle
appears at the interrupt output pin (starts HIGH).
It is recommended to set the stop counting flag of the
control/status register before loading the actual time into
the counters. Loading of illegal states may lead to a
temporary clock malfunction.
1997 Jul 15
12

12 Page





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