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H57V2562GTR Schematic ( PDF Datasheet ) - Hynix Semiconductor

Teilenummer H57V2562GTR
Beschreibung 256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
Hersteller Hynix Semiconductor
Logo Hynix Semiconductor Logo 




Gesamt 23 Seiten
H57V2562GTR Datasheet, Funktion
256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
www.DataSheet4U.com
256M (16Mx16bit) Hynix SDRAM
Memory
Memory Cell Array
- Organized as 4banks of 4,194,304 x 16
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.0 / Aug. 2009
1






H57V2562GTR Datasheet, Funktion
111www.DataSheet4U.com
Synchronous DRAM Memory 256Mbit
H57V2562GTR Series
54_TSOPII Pin DESCRIPTIONS
SYMBOL
CLK
CKE
CS
BA0, BA1
A0 ~ A12
RAS, CAS, WE
LDQM, UDQM
DQ0 ~ DQ15
VDD / VSS
VDDQ / VSSQ
NC
TYPE
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
I/O
SUPPLY
SUPPLY
-
DESCRIPTION
Clock :
The system clock input. All other inputs are registered to the SDRAM on the rising edge
of CLK
Clock Enable:
Controls internal clock signal and when deactivated, the SDRAM will be one of the states
among power down, suspend or self refresh
Chip Select:
Enables or disables all inputs except CLK, CKE and DQM
Bank Address:
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address: RA0 ~ RA12, Column Address: CA0 ~ CA8
Auto-precharge flag: A10
Command Inputs:
RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask:
Controls output buffers in read mode and masks input data in write mode
Data Input / Output:
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection : These pads should be left unconnected
Rev 1.0 / Aug. 2009
6

6 Page









H57V2562GTR pdf, datenblatt
111w w w . D a t a S h e e t 4 U . c o m
Synchronous DRAM Memory 256Mbit
H57V2562GTR Series
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter
Speed
(MHz)
RAS Cycle Time
Operation
Auto Refresh
RAS to CAS Delay
RAS Active Time
RAS Precharge Time
RAS to RAS Bank Active Delay
CAS to CAS Delay
Write Command to Data-In Delay
Data-in to Precharge Command
Data-In to Active Command
DQM to Data-Out Hi-Z
DQM to Data-In Mask
MRS to New Command
Precharge to Data
Output High-Z
CL = 3
CL = 2
Power Down Exit Time
Self Refresh Exit Time
Refresh Time
tRC
tRRC
tRCD
tRAS
tRP
tRRD
tCCD
tWTL
tDPL
tDAL
tDQZ
tDQM
tMRD
tPROZ3
tPROZ2
tDPE
tSRE
tREF
200
Min Max
55 -
55 -
15 -
38.7 100K
15 -
10 -
1-
0-
2-
2-
0-
2-
3-
--
1-
1-
- 64
166
Min Max
60 -
60 -
18 -
42 100K
18 -
12 -
1-
0-
2-
tDPL + tRP
2-
0-
2-
3-
--
1-
1-
- 64
133
Min Max
63 -
63 -
20 -
42 100K
20 -
15 -
1-
0-
2-
2-
0-
2-
3-
2-
1-
1-
- 64
Unit
ns
ns
ns
ns
ns
ns
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
ms
Note
1
Note: 1. A new command can be given tRC after self refresh exit.
Rev 1.0 / Aug. 2009
12

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