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NB3N3002 Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer NB3N3002
Beschreibung HCSL Clock Generator
Hersteller ON Semiconductor
Logo ON Semiconductor Logo 




Gesamt 8 Seiten
NB3N3002 Datasheet, Funktion
NB3N3002
3.3V, Crystal to 25MHz,
100MHz, 125MHz and
200MHz HCSL Clock
Generator
Description
The NB3N3002 is a precision, low phase noise clock generator that
supports PCIExpress and Ethernet requirements. The device accepts
a 25 MHz fundamental mode parallel resonant crystal and generates a
differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz
clock frequencies. Outputs can interface with LVDS with proper
termination (See Figure 5).
This device is housed in 5.0 mm x 4.4 mm narrow body TSSOP 16
pin package.
Features
Uses 25 MHz Fundamental Mode Parallel Resonant Crystal
External Loop Filter is Not Required
HCSL Differential Output or LVDS with Proper Termination
For Selectable Multipliers of the Input Frequency
Output Enable with TriState Outputs
PCIe Gen1, Gen2, Gen3 Jitter Compliant
Typical TIE RMS jitter of 2.5 ps
Phase Noise: @ 100 MHz
Offset Noise Power
100 Hz 109.4 dBc
1 kHz 127.8 dBc
10 kHz 136.2 dBc
100 kHz 138.8 dBc
1 MHz 138.2 dBc
10 MHz 161.4 dBc
20 MHz 163.00 dBc
Operating Range 3.3 V ±5%
Industrial Temperature Range 40°C to +85°C
These are PbFree Devices
http://onsemi.com
16
1
TSSOP16
DT SUFFIX
CASE 948F
MARKING
DIAGRAM
16
NB3N
3002
ALYWG
1G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(*Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
VDD
X1/CLK
25 MHz Clock or
Crystal X2
Clock Buffer
Crystal Oscillator
Phase
Detector
BM
Charge
Pump
VCO
HSCL
Output
CLK
CLK
GND
SEL0
Figure 1. NB3N3002 Simplified Logic Diagram
SEL1 OE IREF
© Semiconductor Components Industries, LLC, 2013
October, 2013 Rev. 6
1
Publication Order Number:
NB3N3002/D






NB3N3002 Datasheet, Funktion
NB3N3002
Qx
HCSL
Driver
Qx
IREF
RREF = 475 W
Zo = 50 W
Zo = 50 W
100 W
RL = 150 W
100 W
LVDS
Receiver
RL = 150 W
Figure 5. HCSL Interface Termination to LVDS
ORDERING INFORMATION
Device
Package
Shipping
NB3N3002DTG
TSSOP16
(PbFree)
96 Units / Rail
NB3N3002DTR2G
TSSOP16
(PbFree)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
6

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