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73S1217F Schematic ( PDF Datasheet ) - Teridian Semiconductor

Teilenummer 73S1217F
Beschreibung Bus-Powered 80515 System-on-Chip
Hersteller Teridian Semiconductor
Logo Teridian Semiconductor Logo 




Gesamt 30 Seiten
73S1217F Datasheet, Funktion
73S1217Fwww.DataSheet4U.com
Bus-Powered 80515 System-on-Chip with USB,
ISO 7816 / EMV, PINpad and More
Simplifying System Integration™
DATA SHEET
December 2008
GENERAL DESCRIPTION
The Teridian Semiconductor Corporation 73S1217F is a
versatile and economical CMOS System-on-Chip device
intended for smart card reader applications. The circuit
features an ISO-7816 / EMV interface, an USB 2.0
interface (full-speed 12Mbps - slave) and a 5x6 PINpad
interface. Additional features include 8 user I/Os,
multiple interrupt options and an analog voltage input (for
DC voltage monitoring such as battery level detection).
Other built-in interfaces include an asynchronous serial
and an I2C interface.
The System-on-Chip is built around an 80515 high-
performance core. Its feature and instruction set is
compatible with the industry standard 8051, while
offering one clock-cycle per instruction processing
power (most instructions). With a CPU clock running up
to 24MHz, it results in up to 20MIPS available that
meets the requirements of various encryption needs
such as AES, DES / 3-DES and even RSA (for PIN
encryption for instance). The circuit requires a single 6
to 12 MHz crystal. An optional 32kHz crystal can be
connected to a sub-system oscillator with a real-time-
clock counter to enable stand-alone applications to
access an RTC value.
The respective 73S1217F embedded memories are;
64KB Flash program memory, 2KB user XRAM
memory, and 256B IRAM memory. On top of these
memories are added independent FIFOs dedicated to
the ISO7816 UART and to the USB interface.
The chip incorporates an inductor-based DC-DC
converter that generates all the necessary voltages to
the various 73S1217F function blocks (smart card
interface, digital core, etc.) from any of two distinct
power supply sources: The +5V USB bus (VBUS, 4.4V to
6.5V), or a main battery (VBAT, 4.0V to 6.5V). The chip
automatically powers-up the DC-DC converter with VBUS
if it is present, or uses VBAT as the supply input.
Alternatively, the pin VPC can support a wider power
supply input range (2.7V to 6.5V), when using a single
system supply source.
In addition, the circuit features an ON/OFF mode which
operates directly with an ON/OFF system switch: Any
activity on the ON/OFF button is debounced internally
and controls the power generation circuit accordingly,
under the supervision of the firmware (OFF request /
OFF acknowledgement at firmware level). The OFF
mode can be alternatively initiated from the controller
(firmware action instead of ON/OFF switch).
In OFF mode, the circuit typically draws less than 1μA,
which makes it ideal for applications where battery life
must be maximized.
Wake-up of the controller upon USB cable insertion is
supported.
Embedded Flash memory is in-system programmable
and lockable by means of on-silicon fuses. This makes
the Teridian 73S1217F suitable for both development and
production phases.
Teridian Semiconductor Corporation offers with its
73S1217F a very comprehensive set of software libraries,
including the smart card and USB protocol layers that are
pre-approved against USB, Microsoft WHQL and EMV,
as well as a CCID reference design. Refer to the
Teridian Semiconductor Corporation 73S12xxF Software
User’s Guide for a complete description of the Application
Programming Interface (API Libraries) and related
Software modules.
A complete array of development and programming
tools, libraries and demonstration boards enable
rapid development and certification of readers that
meet most demanding smart card standards.
APPLICATIONS
Hand-held PINpad smart card readers:
With USB or serial connectivity
Ideal for E-banking (MasterCard CAP, etc) and Digital
Identification (Secure Login, Gov’t ID...)
Transparent USB card readers and USB keys
General purpose smart card readers
ADVANTAGES
Reduced BOM
Larger built-in Flash / RAM than its competitors
Higher performance CPU core (up to 24MIPS)
On-chip DC-DC converter and CMOS switches for
battery and USB power
Sub-μA Power Down mode with ON/OFF switch
Powerful In-Circuit Emulation and Programming
A complete set of EMV4.1, USB and CCID libraries
Overall, the ideal compromise cost / features for high
volume, PINpad reader applications!
Rev. 1.2
© 2008 Teridian Semiconductor Corporation
1






73S1217F Datasheet, Funktion
73S1217F Data Sheet
DSw_w1w2.D1a7taFS_he0e0t42U.com
Table 58: The INT5Ctl Register .................................................................................................................. 56 
Table 59: The ACOMP Register ................................................................................................................. 57 
Table 60: The INT6Ctl Register .................................................................................................................. 58 
Table 61: The LEDCtl Register ................................................................................................................... 59 
Table 62: The DAR Register....................................................................................................................... 63 
Table 63: The WDR Register...................................................................................................................... 63 
Table 64: The SWDR Register ................................................................................................................... 64 
Table 65: The RDR Register....................................................................................................................... 64 
Table 66: The SRDR Register .................................................................................................................... 65 
Table 67: The CSR Register....................................................................................................................... 65 
Table 68: The INT6Ctl Register .................................................................................................................. 66 
Table 69: The KCOL Register..................................................................................................................... 70 
Table 70: The KROW Register ................................................................................................................... 70 
Table 71: The KSCAN Register .................................................................................................................. 71 
Table 72: The KSTAT Register................................................................................................................... 72 
Table 73: The KSIZE Register .................................................................................................................... 73 
Table 74: The KORDERL Register ............................................................................................................. 73 
Table 75: The KORDERH Register ............................................................................................................ 74 
Table 76: The INT5Ctl Register .................................................................................................................. 74 
Table 77: The MISCtl1 Register.................................................................................................................. 76 
Table 78: The CKCON Register ................................................................................................................. 77 
Table 79: The SCSel Register .................................................................................................................... 89 
Table 80: The SCInt Register ..................................................................................................................... 90 
Table 81: The SCIE Register ...................................................................................................................... 91 
Table 82: The VccCtl Register .................................................................................................................... 92 
Table 83: The VccTmr Register .................................................................................................................. 93 
Table 84: The CRDCtl Register .................................................................................................................. 94 
Table 85: The STXCtl Register ................................................................................................................... 95 
Table 86: The STXData Register................................................................................................................ 96 
Table 87: The SRXCtl Register................................................................................................................... 97 
Table 88: The SRXData Register ............................................................................................................... 98 
Table 89: The SCCtl Register ..................................................................................................................... 99 
Table 90: The SCECtl Register................................................................................................................. 100 
Table 91: The SCDIR Register ................................................................................................................. 101 
Table 92: The SPrtcol Register................................................................................................................. 102 
Table 93: The SCCLK Register ................................................................................................................ 103 
Table 94: The SCECLK Register .............................................................................................................. 103 
Table 95: The SParCtl Register ................................................................................................................ 104 
Table 96: The SByteCtl Register .............................................................................................................. 105 
Table 97: The FDReg Register ................................................................................................................. 106 
Table 98: Divider Ratios Provided by the ETU Counter ........................................................................... 106 
Table 99: Divider Values for the ETU Clock ............................................................................................. 107 
Table 100: The CRCMsB Register ........................................................................................................... 108 
Table 101: The CRCLsB Register ............................................................................................................ 108 
Table 102: The BGT Register ................................................................................................................... 109 
Table 103: The EGT Register ................................................................................................................... 109 
Table 104: The BWTB0 Register .............................................................................................................. 110 
Table 105: The BWTB1 Register .............................................................................................................. 110 
Table 106: The BWTB2 Register .............................................................................................................. 110 
Table 107: The BWTB3 Register .............................................................................................................. 110 
Table 108: The CWTB0 Register.............................................................................................................. 110 
Table 109: The CWTB1 Register.............................................................................................................. 110 
Table 110: The ATRLsB Register ............................................................................................................. 111 
Table 111: The ATRMsB Register ............................................................................................................ 111 
Table 112: The STSTO Register .............................................................................................................. 111 
Table 113: The RLength Register............................................................................................................. 111 
Table 114: Smart Card SFR Table ........................................................................................................... 112 
Table 115: The VDDFCtl Register ............................................................................................................ 113 
Table 116: Order Numbers and Packaging Marks ................................................................................... 137 
6 Rev. 1.2

6 Page









73S1217F pdf, datenblatt
73S1217F Data Sheet
DSw_w1w2.D1a7taFS_he0e0t42U.com
Program Memory: The 80515 can address up to 64KB of program memory space from 0x0000 to
0xFFFF. Program memory is read when the MPU fetches instructions or performs a MOVC operation.
After reset, the MPU starts program execution from location 0x0000. The lower part of the program
memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting
from 0x0003. Reset is located at 0x0000.
Flash Memory: The program memory consists of flash memory. The flash memory is intended to
primarily contain MPU program code. Flash erasure is initiated by writing a specific data pattern to
specific SFR registers in the proper sequence. These special pattern/sequence requirements prevent
inadvertent erasure of the flash memory.
The mass erase sequence is:
1. Write 1 to the FLSH_MEEN bit in the FLSHCTL register (SFR address 0xB2[1]).
2. Write pattern 0xAA to ERASE (SFR address 0x94)
Note: The mass erase cycle can only be initiated when the ICE port is enabled.
The page erase sequence is:
1. Write the page address to PGADDR (SFR address 0xB7[7:1])
2. Write pattern 0x55 to ERASE (SFR address 0x94)
The PGADDR register denotes the page address for page erase. The page size is 512 (200h) bytes and
there are 128 pages within the flash memory. The PGADDR denotes the upper seven bits of the flash
memory address such that bit 7:1 of the PGADDR corresponds to bit 15:9 of the flash memory address.
Bit 0 of the PGADDR is not used and is ignored. The MPU may write to the flash memory. This is one of
the non-volatile storage options available to the user. The FLSHCTL SFR bit FLSH_PWE (flash program
write enable) differentiates 80515 data store instructions (MOVX@DPTR,A) between Flash and XRAM
writes. Before setting FLSH_PWE, all interrupts need to be disabled by setting EAL = 1. Table 3 shows
the location and description of the 73S1217F flash-specific SFRs.
Any flash modifications must set the CPUCLK to operate at 3.6923 MHz (MPUCLKCtl = 0x0C)
before any flash memory operations are executed to insure the proper timing when modifying the
flash memory.
12 Rev. 1.2

12 Page





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