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R8830 Schematic ( PDF Datasheet ) - RDC

Teilenummer R8830
Beschreibung 16-BIT RISC MICROCONTROLLER User Manual
Hersteller RDC
Logo RDC Logo 




Gesamt 30 Seiten
R8830 Datasheet, Funktion
RDC®
RISC DSP Controller
www.DataSheet4U.com
R8830
R8830
16-Bit RISC Microcontroller User’s Manual
RDC RISC DSP Controller
RDC Semiconductor Co., Ltd
http:\\www.rdc.com.tw
Tel. 886-3-666-2866
Fax 886-3-563-1498
RDC Semiconductor Co.
Subject to change without notice
1
Final Version 1.9
January 5, 2004






R8830 Datasheet, Funktion
RDC®
RISC DSP Controller
www.DataSheet4U.com
R8830
16-Bit Microcontroller with 8-bit external data bus
1. Features
RISC architecture
Static Design & Synthesizable design
Bus interface
- Multiplexed address and Data bus which
is compatible with 80C188 microprocessor
- Supports non-multiplexed address bus [A19:A0]
- 1M-Byte memory address space
- 64K-byte I/O space
Software compatible with the 80C186
Supports two Asynchronous serial channels with
hardware handshaking signals.
Supports serial ports with DMA transfers
Supports CPU ID
Supports 32 PIO pins
PSRAM (Pseudo static RAM) interface with
auto-refresh control
Three independent 16-bit timers and one
independent watchdog timer
The Interrupt controller with seven maskable
external interrupts and one non-maskable
external interrupt
Two independent DMA channels
Programmable chip-select logic for Memory
or I/O bus cycle decoder
Programmable wait-state generator
RDC Semiconductor Co.
Subject to change without notice
6
Final Version 1.9
January 5, 2004

6 Page









R8830 pdf, datenblatt
RDC®
RISC DSP Controller
4 RFSH2 / ADEN
5 WR
6 RD
7 ALE
8 ARDY
9 S2
10 S1
11 S0
19
20
22
23-37
39, 40
78,80,82,84,
86,
A19/PIO9
A18/PIO8
A17/PIO7
A16-A2
A1, A0
AD0-AD7
RDC Semiconductor Co.
Subject to change without notice
www.DataSheet4U.com
R8830
Bus Interface
For RFSH2 feature, this pin is active low to indicate a
DRAM refresh bus cycle.
For ADEN feature, when this pin is held high on power-on
reset, the address portion of the AD bus can be disabled or
Output/Input enabled by the DA bit in the LMCS and UMCS register during
LCS or UCS bus cycle access. The RFSH2 / ADEN is with a
weak internal pull-up resistor, so no external pull-up resistor is
required. The AD bus always drives both address and data
during LCS or UCS bus cycle access if the RFSH2 / ADEN
pin is with an external pull-low resistor during reset.
Write strobe. This pin indicates that the data on the bus is to be
Output
Output
Output
Input
written into a memory or an I/O device. WR is active during
T2, T3 and Tw of any write cycle, floating during a bus hold or
reset.
Read Strobe. It's an active low signal which indicates that the
microcontroller is performing a memory or I/O read cycle.
RD is floating during a bus hold or reset.
Addressed latch enable. Active high. This pin indicates that an
address output on the AD bus. Address is guaranteed to be
valid on the trailing edge of ALE. This pin is tri-stated during
ONCE mode and is never floating during a bus hold or reset.
Asynchronous ready. This pin performs the microcontroller
that the address memory space or I/O device will complete a
data transfer. The ARDY pin accepts a rising edge that is
asynchronous to CLKOUTA and is active high. The falling
edge of ARDY must be synchronized to CLKOUTA. Tie
ARDY high, so the microcontroller is always asserted in the
ready condition. If the ARDY is not used, tie this pin low to
yield control to SRDY.
Both SRDY and ARDY should be tied to high if the system
need not assert wait states by externality.
Bus cycle status. These pins are encoded to indicate the bus
status. S2 can be used as memory or I/O indicator. S1 can
be used as DT/ R indicator. These pins are floating during
hold and reset.
Bus Cycle Encoding Description
Output
S2 S1 S0
Bus Cycle
0 0 0 Interrupt acknowledge
0 0 1 Read data from I/O
0 1 0 Write data to I/O
0 1 1 Halt
1 0 0 Instruction fetch
1 0 1 Read data from memory
1 1 0 Write data to memory
1 1 1 Passive
Address bus. Non-multiplexed memory or I/O address. The A
Output/Input bus is one-half of a CLKOUTA period earlier than the AD bus.
These pins are high-impedance during a bus hold or reset.
Input/Output
The multiplexed address and data bus for
accessing. The address is present during the t1
memory or
clock phase,
I/O
and
Final Version 1.9
January 5, 2004
12

12 Page





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