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73S8009CN Schematic ( PDF Datasheet ) - Teridian Semiconductor

Teilenummer 73S8009CN
Beschreibung Combo ISO-7816 and USB Universal Smart Card Interface IC
Hersteller Teridian Semiconductor
Logo Teridian Semiconductor Logo 




Gesamt 30 Seiten
73S8009CN Datasheet, Funktion
Simplifying System Integration™
DS_8009C_026
73S8009CNwww.DataSheet4U.com
Combo ISO-7816 and USB Universal
Smart Card Interface IC
DATA SHEET
August 2009
DESCRIPTION
The Teridian 73S8009CN is the world’s first
single-chip smart card electrical interface circuit that
supports all types of smart cards: 5V, 3V and 1.8V,
including traditional ISO-7816-3 asynchronous and
synchronous type 1 and type 2, as well as USB,
ISO-7816-12 cards.
The 73S8009CN is ideally suited for applications
such as desktop computers, laptops and general
purpose smart card readers that require low power
operation from a single 2.7V to 6.5V power supply
voltage source. A power down mode (“OFF” mode)
is available and exhibits a 10nA typical current
consumption.
The circuit provides control, conversion and regulation
of power for the smart card. In addition, the circuit
provides a 3.3V-regulated voltage that is used as an
internal digital supply voltage to the host interface. It is
also made available to supply power to some external
circuitry (a host controller for instance).
For asynchronous and synchronous smart card
operation, the signals for RST, CLK, I/O and auxiliary
signals AUX1 and AUX2 are directly controlled from
the host processor and are level-shifted by the circuit
to the selected VCC value. For more design flexibility,
the host processor is responsible for handling the
signal timing for smart card activation and de-
activation under normal conditions.
The power management circuitry allows operation
from a single power supply source VPC (2.7V to 6.5V).
VPC is converted using an inductive, step-up power
converter to the intermediate voltage, VP. VP is used
by linear voltage regulators and switches internal to
the IC to create the voltages VDD and as required,
VCC. VDD is used by the 73S8009CN and is also
made available for the companion host processor
circuit or for other external circuits.
The 73S8009CN features an ON/OFF pin suitable to
connect to a “push-on/push-off” main system switch.
When the 73S8009CN is “OFF,” the typical current
drawn from VPC is 10nA. For applications that do
not implement any ON/OFF system switch, the
ON/OFF input pin can be driven from a digital output
of the host processor.
FEATURES
Smart Card Interface:
Smart card voltage VCC:
o Selectable: 1.8V, 3V or 5V
o Generated by an internal voltage regulator
o Provides up to 65mA to 3V and 5V cards
and up to 40mA to 1.8V cards
ISO-7816-3 card emergency deactivation
Voltage supervisor detects voltage drop on
VCC (card supply)
True card over-current detection 150mA max.
1 input for a card presence detection switch
Auxiliary I/O lines for synchronous and
ISO-7816-12 USB card support
Proper isolation of smart card signals
depending on smart card type
Card CLK clock frequency up to 20MHz
6kV ESD and short circuit protection on the
card interface
System Controller Interface:
Digital logic level: 3.3V
5 signal images of the card signals (RSTIN,
CLKIN, I/OUC, AUX1UC and AUX2UC)
1 control signal to switch between
synchronous / asynchronous and
ISO-7816-12 USB smart card modes
2 inputs activate and select the card voltage
(CMDVCC% and CMDVCC#)
2 outputs, interrupt to the system controller
(OFF and RDY), to inform the system
controller of the card presence / faults and
status of the interface
1 Chip Select input
2 handshaking signals (OFF_REQ,
OFF_ACK) for proper shutdown sequencing
of all smart card signals
ON/OFF Input for a Main System Switch
DC-DC Step-up Converter:
Generates an intermediary voltage VP
Requires a single 10µH Inductor (rated for
400mA maximum peak current)
VDD power supply output available to power up
external circuitry: 3.3V ±0.3V, 40mA
Industrial temperature range (-40 °C to +85 °C)
Small format QFN32 package: 5x5mm
RoHS compliant (6/6) lead-free package
Rev. 1.4
© 2009 Teridian Semiconductor Corporation
1






73S8009CN Datasheet, Funktion
73S8009CN Data Sheet
DS_w8w00w9.DCatNaS_he0e2t46U.com
Pin
Name
CLK
Pin
Number
Type
16 O
PRES
14 I
VCC
19 PSO
GND
17 GND
Host Processor Interface
CS 12 I
OFF
32 O
I/OUC
AUX1UC
1 IO
2 IO
AUX2UC
3 IO
SC/USB
13 I
DP 25 IO
Equivalent
Circuit
Figure 15
Figure 19
Figure 13
Figure 19
Figure 12
Figure 18
Figure 18
Figure 18
Figure 19
Figure 14
Description
Card clock: provides clock signal (CLK) to card. CLK
is the pass through of the signal on pin CLKIN.
Internal control logic will hold CLK low when card is
not activated or VCC is too low. Will be tri-stated
when SC/USB is set low.
Smart card Presence switch: Active high indicates
card is present.
Smart card activation will not be permitted unless
PRES is active.
Card power supply – logically controlled by
sequencer, output of LDO regulator. Requires an
external 0.47uF low ESR filter capacitor to GND.
Card ground.
Chip Select. When CS = 1, the control and signal
pins are configured normally. When CS is set low,
CMDVCC%, RSTIN, and CMDVCC# are latched.
I/OUC, AUX1UC, and AUX2UC are set to
high-impedance pull-up mode and do not pass data
to or from the smart card. Signals RDY and OFF are
disabled to prevent a low output and the internal
pull-up resistors are disconnected. Should be tied to
VDD when a single 73S8009CN is used.
Interrupt signal to the processor. Active Low -
Multi-function indicating fault conditions and card
presence. Open drain output configuration – It
includes an internal 20kΩ pull-up to VDD. Pull-up is
disabled in Power down state and CS = 0 modes.
System controller data I/O to/from the card. Includes
an 11kΩ pull-up resistor to VDD.
System controller auxiliary data I/O to/from the card
for synchronous / asynchronous operation mode.
Connection to AUX1 is opened when SC/USB is low.
Includes an 11kΩ pull-up resistor to VDD.
System controller auxiliary data I/O to/from the card
for synchronous / asynchronous operation mode.
Connection to AUX2 is opened when SC/USB is low.
Includes an 11kΩ pull-up resistor to VDD.
Smart Card Interface enable, USB interface disable.
Pin is provided with a weak pull-up.
When high, the 73S8009CN operates in
synchronous / asynchronous operation mode.
When low, CLK, RST I/O, AUX1, and AUX2 are
tri-stated. Pin AUX1 is connected to pin DP and pin
AUX2 is connected to pin DM.
USB D+ connection to / from USB controller.
When SC/USB is set low, this pin is electrically
connected to the AUX1 pin, otherwise it is isolated.
6 Rev. 1.4

6 Page









73S8009CN pdf, datenblatt
73S8009CN Data Sheet
DS_w8w00w9.DCatNaS_he0e2t46U.com
Symbol
Parameter
Condition
Reset and Clock for card interface, RST, CLK
VOH Output level, high
IOH =-200µA
VOL Output level, low
IOL=200µA
VINACT
Ifloat
Output voltage when
outside of session
Input current
IRST_LIM
ICLK_LIM
tR, tF
Output current limit, RST
Output current limit, CLK
Output rise time, fall time
δ Duty cycle for CLK
IOL = 0
IOL = 1mA
Input current with SC/USB =
0, open circuited
CL = 35pF for CLK, 10% to
90%
CL = 200pF for RST, 10% to
90%
CL =35pF, FCLK 20MHz,
CLKIN duty cycle is 48% to
52%.
Min Nom Max
0.9 * VCC
0
-5
45
VCC
0.15
*VCC
0.1
0.3
+5
30
70
12
100
55
Unit
V
V
V
V
µA
mA
mA
ns
ns
%
2.4 Digital Signals Characteristics
Table 5 lists the 73S8009CN digital signals characteristics.
Table 5: Digital Signals Characteristics
Symbol Parameter
Condition
Min Nom Max
Unit
Digital I/O
(except for I/OUC, AUX1UC, AUX2UC; see Smart Card Interface Requirements for those specifications)
VIL
VILOFFACK
Input Low Voltage
Input low voltage for
OFF_ACK pin
-0.3 0.8
OFF_REQ pin = VDD
-0.3
0.7
V
V
VIH
VOL
VOH
ROUT
Input High Voltage
Output Low Voltage
Output High Voltage
Pull-up resistor; OFF, RDY
IOL = 2mA
IOH = -1mA
1.8 VDD + 0.3
0.45
VDD - 0.45
14 20 26
V
V
V
k
RACK
Resistor between
OFF_REQ and 0FF_ACK
70 100 130
k
|IIL1|
Input Leakage Current
GND < VIN < VDD
tSL Time from CS goes high to
interface active
–5
50 – –
μA
ns
tDZ Time from CS goes low to
interface inactive, Hi-Z
50 – –
ns
tIS Set-up time, control
signals to CS rising edge
50 – –
ns
tSI Hold time, control signals
from CS rising edge
50 ns
tID Set-up time, control
signals to CS fall
50 – –
ns
tDI Hold time, control signals
from CS fall
– – 50 ns
12 Rev. 1.4

12 Page





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