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73M1903 Schematic ( PDF Datasheet ) - TDK Semiconductor

Teilenummer 73M1903
Beschreibung Modem Analog Front End
Hersteller TDK Semiconductor
Logo TDK Semiconductor Logo 




Gesamt 30 Seiten
73M1903 Datasheet, Funktion
DESCRIPTION
The TDK 73M1903 Analog Front End (AFE) IC
includes fully differential hybrid driver outputs,
which connect to the telephone line interface
through a transformer-based DAA. The receive
pins are also fully differential for maximum
flexibility and performance. This arrangement
allows for the design of a high performance
hybrid circuit to improve signal to noise
performance under low receive level conditions,
and compatibility with any standard transformer
intended for PSTN communications applications.
The device incorporates a programmable
sample rate circuit to support soft modem and
DSP based implementations of all speeds up to
V.92 (56Kbps). The sampling rates supported
are from 7.2kHz to 14.4kHz by programming
pre-scaler NCO and PLL NCO.
The TDK 73M1903 device incorporates a digital
host interface that is compatible with the serial
ports found on most commercially available
DSPs and processors and exchanges both
payload and control information with the host.
Cost saving features of the device include an
input reference frequency circuit, which accepts
a range of crystals from 9-27MHz. It also
accepts external reference clock values between
9-40MHz generated by the host processor. In
most applications, this eliminates the need for a
dedicated crystal oscillator and reduces the bill
of material (BOM).
The 73M1903 also supports two analog loop
back and one digital loop back test modes.
The 73M1903 in 32-TQFP package is footprint
compatible with 73M2901CL embedded modem
and allows for the same circuit design to
accommodate soft modem, V.22bis hard
modem, and high speed (V.32bis/V.34/V.92)
applications through population of an external
data pump device.
73M1903
Modem Analog Front End
PRODUCT DATA SHEET
JANUARY 2004
FEATURES
Up to 56Kbps (V.92) performance
Programmable sample rates (7.2 - 14.4kHz)
Reference clock range of 9-40MHz
Crystal frequency range of 9-27MHZ
Host synchronous serial interface operation
Pin compatible with 73M2901CL modem
Low power modes
On board line interface drivers
Fully differential receiver and transmitter
Drivers for transformer interface
3.0V – 3.6V operation
5V tolerant I/O
Industrial temperature range (-40 to +85°C)
JATE compliant transmit spectrum
Package options: 32-TQFP and 32-MLF
APPLICATIONS
Set Top Boxes
Personal Video Recorders (PVR)
Multifunction Peripherals (MFP)
Fax Machines
Internet Appliances
Game Consoles
Point of Sale Terminals
Automatic Teller Machines
Speaker Phones
RF Modems
TXAP
TXAN
(HYBRID)
Transmit
Drivers/
Filters
Analog
Sigma
Delta
VBG
Ref.
RXAP
RXAN
Receive
Mux/
Filters
Control Serial
DAC Registers Port
GPIO
HOOK
DAA
Controls Clocks
Control
Logic
Crystal
SCLK
SDIN
SDOUT
FSB
http://www.tdksemiconductor.com TDK SEMICONDUCTOR CONFIDENTIAL
1/08/04 R4.031






73M1903 Datasheet, Funktion
73M1903
Modem Analog Front End
PRODUCT DATA SHEET
http://www.tdksemiconductor.com TDK SEMICONDUCTOR CONFIDENTIAL
6 / 46
1/08/04 R4.031

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73M1903 pdf, datenblatt
73M1903
Modem Analog Front End
PRODUCT DATA SHEET
GPIO
The TDK 73M1903 modem AFE device provides 8 user defined I/O pins. Each pin is programmed
separately as either an input or an output by a bit in a direction register. If the bit in the direction register is
set high, the corresponding pin is an input whose value is read from the GPIO data register. If it is low, the
pin will be treated as an output whose value is set by the GPIO data register.
To avoid unwanted current contention and consumption in the system from the GPIO port before the
GPIO is configured after a reset, the GPIO port I/Os are initialized to a high impedance state. The input
structures are protected from floating inputs, and no output levels are driven by any of the GPIO pins.
The GPIO pins are configured as inputs or outputs when the host controller (or DSP) writes to the GPIO
direction register. The GPIO direction and data registers are initialized to all ones (FFh) upon reset.
GPIO Data (GPIO): Address 02h
Reset State FFh
BIT 7
BIT 6
GPIO7 GPIO6
BIT 5
GPIO5
BIT 4
GPIO4
BIT 3
GPIO3
BIT 2
GPIO2
BIT 1
GPIO1
BIT 0
GPIO0
Bits in this register will be asserted on the GPIO(7:0) pins if the corresponding direction register bit is a 0.
Reading this address will return data reflecting the values of pins GPIO(7:0).
GPIO Direction (DIR): Address 03h
Reset State FFh
BIT 7
BIT 6
DIR7
DIR6
BIT 5
DIR5
BIT 4
DIR4
BIT 3
DIR3
BIT 2
DIR2
BIT 1
DIR1
BIT 0
DIR0
This register is used to designate the GPIO pins as either inputs or outputs. If the register bit is low, the
corresponding GPIO pin is programmed as an output. If the register bit is a 1, the corresponding pin will
be treated as an input.
ANALOG I/O
Figure 4 on page 12 shows the block diagram of the analog front end. The analog interface circuit uses
differential transmit and receive signals to and from the external circuitry.
The hybrid driver in the TDK 73M1903 IC is capable of connecting directly, but not limited to, a
transformer-based Direct Access Arrangement (DAA). The hybrid driver is capable of driving the DAA’s
line coupling transformer, which carries an impedance on the primary side that is typically rated at 600O,
depending on the transformer and matching network. The hybrid drivers can also drive high impedance
loads without modification. The class AB behavior of the amplifiers provides load dependent power
consumption.
http://www.tdksemiconductor.com TDK SEMICONDUCTOR CONFIDENTIAL
12 / 46
1/08/04 R4.031

12 Page





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