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PDF MC100EP196B Data sheet ( Hoja de datos )
| Número de pieza | MC100EP196B | |
| Descripción | 3.3 V ECL Programmable Delay Chip | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC100EP196B
3.3 V ECL Programmable
Delay Chip With FTUNE
Descriptions
The MC100EP196B is a Programmable Delay Chip (PDC) designed
primarily for clock deskewing and timing adjustment. It provides variable
delay of a differential NECL/PECL input transition. It has similar
architecture to the EP195 with the added feature of further tunability in
delay using the FTUNE pin. The FTUNE input takes an analog voltage
from VCC to VEE to fine tune the output delay from 0 to 60 ps.
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 3. The delay
increment of the EP196B has a digitally selectable resolution of about
10 ps and a net range of up to 10.4 ns. The required delay is selected by
the 10 data select inputs D[9:0] values and controlled by the LEN
(Pin 10). A LOW level on LEN allows a transparent LOAD mode of
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
will LOCK and HOLD current values present against any subsequent
changes in D[10:0]. The approximate delay values for varying tap
numbers correlating to D0 (LSB) through D9 (MSB) are shown in
Table 6 and Figure 4.
The IN/IN inputs can accept LVPECL (SE or Diff), or LVDS level
signals. Because the MC100EP196B is designed using a chain of
multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin
D10 is provided for controlling Pins 14 and 15, CASCADE and
CASCADE, also latched by LEN, in cascading multiple PDCs for
increased programmable range. The cascade logic allows full control of
multiple PDCs. Switching devices from all “1” states on D[0:9] with
SETMAX LOW to all “0” states on D[0:9] with SETMAX HIGH will
increase the delay equivalent to “D0”, the minimum increment.
Select input pins D[10:0] may be threshold controlled by
combinations of interconnects between VEF (pin 7) and VCF (pin 8) for
receiving LVCMOS, ECL, or LVTTL level signals. For LVCMOS input
levels, leave VCF and VEF open. For ECL operation, short VCF and VEF
(Pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply
reference to VCF and leave open VEF pin. The 1.5 V reference voltage at
the VCF pin can be accomplished by placing a 2.2 kW resistor between
VCF and VEE for a 3.3 V power supply.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB and
VCC via a 0.01 mF capacitor and limit current sourcing or sinking to
0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
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MARKING
DIAGRAMS*
LQFP−32
FA SUFFIX
CASE 873A
MC100
EP196B
AWLYYWWG
32
1
1 32
QFN32
MN SUFFIX
CASE 488AM
1
MC100
EP196B
ALYWG
G
A = Assembly Location
WL, L = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
Features
• Maximum Input Clock Frequency >1.2 GHz Typical
• Programmable Range: 0 ns to 10 ns
• Delay Range: 2.2 ns to 12.4 ns
• 10 ps Increments
• Linearity ±40 ps max
• PECL Mode Operating Range:
VCC = 3.0 V to 3.6 V with VEE = 0 V
• NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −3.6 V
• IN/IN Inputs Accept LVPECL, LVNECL, LVDS Levels
• A Logic High on the EN Pin Will Force Q to Logic Low
• D[10:0] Can Select Either LVPECL, LVCMOS, or
LVTTL Input Levels
• VBB Output Reference Voltage
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 2
1
Publication Order Number:
MC100EP196B/D
1 page  
MC100EP196B
Figure 3. Logic Diagram
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5
5 Page 
MC100EP196B
IN
IN
Q
Q
tPLH
VINPP = VIH(D) − VIL(D)
VOUTPP = VOH(Q) − VOL(Q)
tPHL
Figure 5. AC Reference Measurement
Using the FTUNE Analog Input
The analog FTUNE pin on the EP196 device is intended
to add more delay in a tunable gate to enhance the 10 ps
resolution capabilities of the fully digital EP196. The level
of resolution obtained is dependent on the voltage applied to
the FTUNE pin.
To provide this further level of resolution, the FTUNE pin
must be capable of adjusting the additional delay finer than
the 10 ps digital resolution (See Logic Diagram). This
requirement is easily achieved because a 60 ps additional
delay can be obtained over the entire FTUNE voltage range
(See Figure 6). This extra analog range ensures that the
FTUNE pin will be capable even under worst case
conditions of covering a digital resolution. Typically, the
analog input will be driven by an external DAC to provide
a digital control with very fine analog output steps. The final
resolution of the device will be dependent on the width of the
DAC chosen.
To determine the voltage range necessary for the FTUNE
input, Figure 6 should be used. There are numerous voltage
ranges which can be used to cover a given delay range; users
are given the flexibility to determine which one best fits their
designs.
90
80
VCC = 0 V
VEE = −3.3 V
70
60
50
−40°C
25°C
40
30
20 85°C
10
0
−10
−3.3 −2.97 −2.64 −2.31 −1.98 −1.65 −1.32 −0.99
VEE FTUNE VOLTAGE (V)
−0.66 −0.33 0
VCC
Figure 6. Typical EP196B Delay versus FTUNE Voltage
Cascading Multiple EP196Bs
To increase the programmable range of the EP196B,
internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple EP196Bs without the
need for any external gating. Furthermore, this capability
requires only one more address line per added EP196B.
Obviously, cascading multiple programmable delay chips
will result in a larger programmable range: however, this
increase is at the expense of a longer minimum delay.
Figure 7 illustrates the interconnect scheme for cascading
two EP196Bs. As can be seen, this scheme can easily be
expanded for larger EP196B chains. The D10 input of the
EP196B is the CASCADE control pin. With the
interconnect scheme of Figure 7 when D10 is asserted, it
signals the need for a larger programmable range than is
achievable with a single device and switches output pin
CASCADE HIGH and pin CASCADE LOW. The A11
address can be added to generate a cascade output for the
next EP196B. For a 2−device configuration, A11 is not
required.
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| PDF Descargar | [ Datasheet MC100EP196B.PDF ] | |
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