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PDF LP61L256B Data sheet ( Hoja de datos )
| Número de pieza | LP61L256B | |
| Descripción | 32K X 8 Bit High SPEED LOW VCC CMOS SRAM | |
| Fabricantes | AMIC Technology | |
| Logotipo |  |
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LP61L256B Series
32K X 8 Bit High SPEED LOW VCC CMOS SRAM
Features
n Single +3.3 volt power supply
n Access times: 12 ns (max.)
n Current: Operating: 100mA (max.)
Standby: 10mA (max.)
n Full static operation, no clock or refreshing required
General Description
The LP61L256B is a high-speed, low-power 262,144-bit
static random access memory organized as 32,768 words
by 8 bits that operates on a single 3.3V power supply.
Input and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
n All inputs and outputs directly TTL compatible
n Common I/O using three-state output
n Data retention voltage: 2V (min.)
n Available in 28-pin SOJ and TSOP packages
Minimum standby power is drawn by this device when CE
is at a high level, independent of the other input levels.
Data retention is guaranteed at a power supply voltage as
low as 2V.
Pin Configurations
n SOJ
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
n TSOP
14 1
15 28
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Pin
Name
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3
Pin No. 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Pin
Name
A2 A1 A0 I/O 1 I/O 2 I/O 3 GND I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 CE A10
(August, 2001, Version 1.0)
1 AMIC Technology, Inc.
1 page  
LP61L256B Series
AC Characteristics (continued)
Symbol
Parameter
LP61L256B-12
Min.
Max.
Unit
Write Cycle
tWC Write Cycle Time
tCW Chip Enable to End of Write
tAS Address Setup Time of Write
tAW Address Valid to End of Write
tWP Write Pulse Width
tWR Write Recovery Time
tWHZ Write to Output in High Z
tDW Data to Write Time Overlap
tDH Data Hold from Write Time
tOW Output Active from End of Write
12 -
10 -
0-
10 -
8-
0-
07
8-
0-
5-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levels.
Timing Waveforms
Read Cycle 1(1, 2, 4)
Address
DOUT
tRC
tAA
tOH
tOH
(August, 2001, Version 1.0)
5 AMIC Technology, Inc.
5 Page 
Package Information
TSOP 28L TYPE I (8 X 13.4mm) Outline Dimensions
D RD
HD
y
Detail "A"
LP61L256B Series
unit: inches/mm
12.0°
GAUGE PLANE
L
LE
Detail "A"
θ
Sb
Symbol
A
A1
A2
b
c
D
E
e
HD
L
LE
S
y
θ
Dimensions in inches
0.049 Max.
0.002 Min.
0.039±0.002
0.0079±0.0012
0.006±0.0003
0.465±0.004
0.315±0.004
0.0217 TYP.
0.528±0.008
0.02±0.008
0.0266 TYP.
0.0167 TYP.
0.004 Max.
0° ~ 6°
Dimensions in mm
1.25 Max.
0.05 Min.
1.00±0.05
0.20±0.03
0.15±0.008
11.80±0.10
8.00±0.10
0.55 TYP.
13.40±0.20
0.50±0.20
0.675 TYP.
0.425 TYP.
0.10 Max.
0° ~ 6°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
(August, 2001, Version 1.0)
11 AMIC Technology, Inc.
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet LP61L256B.PDF ] | |
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