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PDF STM6522 Data sheet ( Hoja de datos )
| Número de pieza | STM6522 | |
| Descripción | Dual push-button Smart Reset | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STM6522
Dual push-button
Smart Reset™ with capacitor-adjustable setup delay
Features
■ Dual Smart Reset™ push-button inputs with
capacitor-adjustable extended reset setup
delay (tSRC)
■ No power-on reset
■ Dual RST output, active-low, open-drain
■ Fixed Smart Reset™ input logic voltage levels
■ Broad operating voltage range 1.65 V to 5.5 V,
inactive reset output levels valid down to 1.0 V
■ Low supply current (1.5 µA)
■ Operating temperature:
industrial grade –40 °C to +85 °C
■ TDFN8 package: 2 mm x 2 mm x 0.75 mm
■ RoHS compliant
Applications
■ Mobile phones, smartphones
■ e-books
■ MP3 players
■ Games
■ Portable navigation devices
■ Any application that requires delayed reset
push-button(s) response for improved system
stability
TDFN8 (DG)
2 mm x 2 mm
May 2010
Doc ID 17045 Rev 2
1/25
www.st.com
1
1 page  
STM6522
1 Description
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Description
The Smart Reset™ devices provide a useful feature that ensures that inadvertent short
reset push-button closures do not cause system resets as the extended Smart Reset™
delay setup periods are implemented. Once the valid Smart Reset™ input levels and setup
delay are met, the device generates an output reset pulse for a fixed timeout period (tREC).
The typical application hookup shows that either a single Smart Reset™ input, or both reset
inputs can be connected to the applications interrupt and control both the interrupt pin and
the hard reset functions. If the push-button is closed for a short time, the processor is only
interrupted. If the system still does not respond properly, holding the push-button(s) for the
extended setup time (tSRC) causes a hard reset of the processor. The Smart Reset™
feature helps significantly increase system stability and eliminates the need for a dedicated
reset button.
The STM65xx family of Smart Reset™ devices consists of low-current microprocessor reset
circuits targeted at applications such as MP3 players, portable navigation or mobile phones,
generally any application that requires delayed reset push-button(s) response for improved
system stability. The devices in the STM65xx Smart Reset™ family include various
combinations of useful features for the targeted applications.
The STM6522 has two combined Smart Reset™ inputs (SR0 and SR1) with delayed reset
setup time (tSRC) programmed by an external capacitor on the SRC pin.
Figure 1. Logic diagram
VCC
SR0
SR1
SRC
STM6522
RST1
RST2
VSS
AM04867v2
Doc ID 17045 Rev 2
5/25
5 Page 
STM6522
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Typical operating characteristics
3 Typical operating characteristics
Figure 8. Supply current (ICC) vs. temperature
3
2.5
2
1.5
1
0.5
0
–60 –40 –20
0
20 40 60 80
Temperature [˚C]
5.5 V 3.3 V 2 V
100 120 140
AM07328
Figure 9.
Smart Reset delay (tSRC) vs. temperature, CSRC = 0.6 µF
9
8.5
8
7.5
7
6.5
6
–60 –40 –20
0
20 40 60
Temperature [˚C]
80
5.5 V 3.3 V
2V
100 120 140
AM07329
Doc ID 17045 Rev 2
11/25
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet STM6522.PDF ] | |
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