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ADM1065 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADM1065
Beschreibung Super Sequencer and Monitor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
ADM1065 Datasheet, Funktion
Data Sheet
FEATURES
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
5 selectable input attenuators allow supervision of supplies to
14.4 V on VH
6 V on VP1 to VP4 (VPx)
5 dual-function inputs, VX1 to VX5 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable driver outputs, PDO1 to PDO10 (PDOx)
Open-collector with external pull-up
Push/pull output driven to VDDCAP or VPx
Open collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 40-lead, 6 mm × 6 mm LFCSP and
48-lead, 7 mm × 7 mm TQFP packages
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
Super Sequencer and Monitor
ADM1065
FUNCTIONAL BLOCK DIAGRAM
REFOUT REFGND SDA SCL A1 A0
ADM1065
VREF
SMBus
INTERFACE
EEPROM
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
AGND
VDDCAP
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
SEQUENCING
ENGINE
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF N-FET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
VDD
ARBITRATOR
VCCP
GND
Figure 1.
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
PDOGND
GENERAL DESCRIPTION
The ADM1065 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple-supply systems.
The device also provides up to 10 programmable inputs for moni-
toring undervoltage faults, overvoltage faults, or out-of-window
faults on up to 10 supplies. In addition, 10 programmable outputs
can be used as logic enables. Six of these programmable outputs
can each provide up to a 12 V output for driving the gate of an
N-FET that can be placed in the path of a supply.
The logical core of the device is a sequencing engine. This state
machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs
based on the condition of the inputs.
The ADM1065 is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can
be programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
For more information about the ADM1065 register map, refer
to the AN-698 Application Note at www.analog.com.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADM1065 Datasheet, Funktion
ADM1065
Data Sheet
Parameter
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode
(PDO1 to PDO6)
Output Impedance
VOH
IOUTAVG
Standard (Digital Output) Mode
(PDO1 to PDO10)
VOH
VOL
IOL2
ISINK2
RPULL-UP
ISOURCE (VPx)2
Min Typ
500
11 12.5
10.5 12
20
2.4
VPU − 0.3
0
16 20
Three-State Output Leakage Current
Oscillator Frequency
DIGITAL INPUTS (VXx, A0, A1)
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Current, IIH
Input Low Current, IIL
Input Capacitance
Programmable Pull-Down Current,
IPULL-DOWN
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH
Input Low Voltage, VIL
Output Low Voltage, VOL2
SERIAL BUS TIMING3
Clock Frequency, fSCLK
Bus Free Time, tBUF
Start Setup Time, tSU;STA
Stop Setup Time, tSU;STO
Start Hold Time, tHD;STA
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
Input Low Current, IIL
SEQUENCING ENGINE TIMING
State Change Time
90
2.0
−1
2.0
1.3
0.6
0.6
0.6
1.3
0.6
100
5
100
5
20
10
Max Unit Test Conditions/Comments
kΩ
14 V IOH = 0 µA
13.5 V IOH = 1 µA
µA 2 V < VOH < 7 V
V VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA
4.5 V VPU to VPx = 6.0 V, IOH = 0 mA
V VPU ≤ 2.7 V, IOH = 0.5 mA
0.50 V IOL = 20 mA
20 mA Maximum sink current per PDO pin
60 mA Maximum total sink for all PDO pins
29 kΩ Internal pull-up
2 mA Current load on any VPx pull-ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
VPx pin
10 µA VPDO = 14.4 V
110 kHz All on-chip time delays derived from this clock
V Maximum VIN = 5.5 V
0.8 V Maximum VIN = 5.5 V
µA VIN = 5.5 V
1 µA VIN = 0 V
pF
µA VDDCAP = 4.75 V, TA = 25°C if known logic state
is required
V
0.8 V
0.4 V IOUT = −3.0 mA
400 kHz
µs
µs
µs
µs
µs
µs
300 ns
300 ns
ns
ns
1 µA VIN = 0 V
µs
1 At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Timing specifications are guaranteed by design and supported by characterization data.
Rev. E | Page 6 of 28

6 Page









ADM1065 pdf, datenblatt
ADM1065
POWERING THE ADM1065
The ADM1065 is powered from the highest voltage input on either
the positive-only supply inputs (VPx) or the high voltage supply
input (VH). This technique offers improved redundancy because
the device is not dependent on any particular voltage rail to keep it
operational. The same pins are used for supply fault detection
(see the Supply Supervision section). A VDD arbitrator on the
device chooses which supply to use. The arbitrator can be
considered an OR’ing of five low dropout regulators (LDOs)
together. A supply comparator chooses the highest input to
provide the on-chip supply. There is minimal switching loss with
this architecture (~0.2 V), resulting in the ability to power the
ADM1065 from a supply as low as 3.0 V. Note that the supply on
the VXx pins cannot be used to power the device.
An external capacitor to GND is required to decouple the on-chip
supply from noise. This capacitor should be connected to the
VDDCAP pin, as shown in Figure 15. The capacitor has another
use during brownouts (momentary loss of power). Under these
conditions, when the input supply (VPx or VH) dips transiently
below VDD, the synchronous rectifier switch immediately turns
off so that it does not pull VDD down. The VDD capacitor can
then act as a reservoir to keep the device active until the next
highest supply takes over the powering of the device. A 10 µF
capacitor is recommended for this reservoir/decoupling function.
The VH input pin can accommodate supplies up to 14.4 V, which
allows the ADM1065 to be powered using a 12 V backplane supply.
In cases where this 12 V supply is hot swapped, it is recommended
that the ADM1065 not be connected directly to the supply. Suitable
precautions, such as the use of a hot swap controller, should be
taken to protect the device from transients that could cause
damage during hot swap events.
Data Sheet
When two or more supplies are within 100 mV of each other,
the supply that first takes control of VDD keeps control. For
example, if VP1 is connected to a 3.3 V supply, VDD powers up
to approximately 3.1 V through VP1. If VP2 is then connected
to another 3.3 V supply, VP1 still powers the device unless VP2
goes 100 mV higher than VP1.
VDDCAP
VP1 IN OUT
4.75V
LDO
EN
VP2 IN OUT
4.75V
LDO
EN
VP3 IN OUT
4.75V
LDO
EN
VP4 IN OUT
4.75V
LDO
EN
INTERNAL
VH
IN OUT
DEVICE
4.75V
SUPPLY
LDO
EN
SUPPLY
COMPARATOR
Figure 15. VDD Arbitrator Operation
SLEW RATE CONSIDERATION
When the ambient temperature of operation is less than
approximately −20°C, and in the event of a power loss where all
supply inputs fail for less than a few hundreds of milliseconds
(for example, due to a system supply brownout), it is recommended
that the supply voltage recovers with a ramp rate of at least
1.5 V/ms or less than 0.5 V/ms.
Rev. E | Page 12 of 28

12 Page





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