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PDF BU7964GUW Data sheet ( Hoja de datos )
| Número de pieza | BU7964GUW | |
| Descripción | Data rate 1350Mbps RGB Interface | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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MSDL (Mobile Shrink Data Link) Transceivers for Mobile Phones
Data rate 1350Mbps
RGB Interface
BU7964GUW
No.10058EAT04
●Description
BU7964GUW is a differential serial interface connecting mobile phone LCD modules to the host CPU. Unique technology is
utilized for lower power consumption and EMI. MSDL minimizes the number of wires required - an important consideration
in hinge phones - resulting in greater reliability and design flexibility.
●Features
1) MSDL3 high-speed differential interface with a maximum transfer rate of 1350 Mbps.
2) Compatible with24-bit RGB video mode for LCD controller-to-LCD interface.
3) Pixel clock frequency range from 4 to 45MHz.
4) Depending on the data transfer rate, either, two or three differential data channels can be selected.
●Applications
Serial Interface for LCD Display Interface of Mobile Devices Application.
●Absolute Maximum Ratings
Parameter
Power Supply Voltage
Input Voltage
Output Voltage
Input Current
Output Current
Preservation Temperature
Symbol
DVDD
MSVDD
VIN
VOUT
IIN
IOUT
Tstg
Ratings
-0.3 ~ +2.5
-0.3 ~ +2.5
-0.3 ~ MSVDD+0.3
-0.3 ~ DVDD+0.3
-0.3 ~ MSVDD+0.3
-0.3 ~ DVDD+0.3
-10 ~ +10
-70 ~ +70
-55 ~ +125
Unit Remarks
V-
V-
V I/O terminals of MSVDD line
V I/O terminals of DVDD line
V I/O terminals of MSVDD line
V I/O terminals of DVDD line
mA -
mA -
℃-
●Operating Conditions
Parameter
Supply Voltage for DVDD
Supply Voltage for MSVDD
Data Transmission Rate
Operating Temperature Range
Symbol
VDVDD
VMSVDD
DR
Topr
Min
1.65
1.65
120
-30
Ratings
Typ
1.80
1.80
-
25
Max
1.95
1.95
450
85
Unit Conditions
V
V
Mbps/ch
℃
VDVDD = VMSVDD
-
-
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© 2010 ROHM Co., Ltd. All rights reserved.
1/18
2010.04 - Rev.A
1 page  
BU7964GUW
●Pin Functions
Power Supply / Ground: 10-pin
Name Width
Table 1. Power Supply and Ground
Functions
DVDD
3 Logic core, CMOS I/O power supply.
MSVDD
2 Analog core power supply.
DGND
3 CMOS I/O and logic core ground.
MSGND
2 Analog core ground.
Technical Note
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High-Speed Serial Interface: 8-pin
Name Width Level I/O
Table 2. MSDL3
Functions
CLK+
1 Analog I CLK+pin.
CLK-
1 Analog I CLK-pin.
D0+ 1 Analog I D0+pin.
D0- 1 Analog I D0-pin.
D1+ 1 Analog I D1+pin.
D1- 1 Analog I D1-pin.
D2+ 1 Analog I D2+pin.
D2- 1 Analog I D2-pin.
Shutdown
Pull Down
Equivalent
Schematic
D
Pull Down
D
Pull Down
D
Pull Down
D
Pull Down
D
Pull Down
D
Pull Down
D
Pull Down
D
Analog: 1-pin
Name Width
Level
DRVR
1 Analog
Table 3. Analog
I/O Functions
-
10kΩ ± 5% register should be connected between
DRVR and MSGND.
Shutdown
-
Equivalent
Schematic
D
Parallel Data Interface: 29-pin
Name Width Level
I/O
Table 4. Parallel Data Interface
Functions
PCLK
1 CMOS O PCLK interface.
Shutdown
‘L’
Equivalent
Schematic
C
PD[26:0] 27 CMOS O Parallel data interface.
CPO
Parity error toggled output, normally ‘L,’ output is
1 CMOS O toggled during one PCLK period when a parity error
is detected
‘L’
‘L’
C
C
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© 2010 ROHM Co., Ltd. All rights reserved.
5/18
2010.04 - Rev.A
5 Page 
BU7964GUW
2) AC Characteristics
Parallel Data Output Timing
P [2 : 0]
Technical Note
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t R _D
t R _D
t R _R,
t R _F
0.7×DVDD
0.5×DVDD
0.3×DVDD
PCL
0.5×DVDD
t R _DUTY
t R _PCLK
Fig.9. Parallel Data Output Timing
Table 12. Parallel Data Output AC Timing
Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted.
Parameter
Limits
Symbol
Min Typ Max
PCLK Output Duty Cycle
Output Data Setup Time
Output Data Hold Time
Output Data Rise Time/Fall time
tRX_DUTY
tRX_DS
tRX_DH
tRX_R
tRX_F
45
0.41X
tRx_PCLK
0.41X
tRx_PCLK
-
-
50
-
-
9
3
55
-
-
-
-
Unit Conditions
% CL=10pF
ns CL=10pF
ns CL=10pF
ns F_XS=0, CL=10pF
ns F_XS=1, CL=10pF
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
11/18
2010.04 - Rev.A
11 Page | ||
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