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LP3985IBL-2.5 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer LP3985IBL-2.5
Beschreibung Micropower/ 150mA Low-Noise Ultra Low-Dropout CMOS Voltage Regulator
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 17 Seiten
LP3985IBL-2.5 Datasheet, Funktion
June 2003
LP3985
Micropower, 150mA Low-Noise Ultra Low-Dropout CMOS
Voltage Regulator
General Description
The LP3985 is designed for portable and wireless applica-
tions with demanding performance and space requirements.
The LP3985 is stable with a small 1µF ±30% ceramic or
high-quality tantalum output capacitor. The micro SMD re-
quires the smallest possible PC board area - the total appli-
cation circuit area can be less than 2.0mm x 2.5mm, a
fraction of a 1206 case size.
The LP3985’s performance is optimized for battery powered
systems to deliver ultra low noise, extremely low dropout
voltage and low quiescent current. Regulator ground current
increases only slightly in dropout, further prolonging the
battery life.
An optional external bypass capacitor reduces the output
noise without slowing down the load transient response.
Fast start-up time is achieved by utilizing an internal
power-on circuit that actively pre-charges the bypass capaci-
tor.
Power supply rejection is better than 50 dB at low frequen-
cies and starts to roll off at 1kHz. High power supply rejection
is maintained down to low input voltage levels common to
battery operated circuits.
The device is ideal for mobile phone and similar battery
powered wireless applications. It provides up to 150 mA,
from a 2.5V to 6V input. The LP3985 consumes less than
1.5µA in disable mode and has fast turn-on time less than
200µs.
The LP3985 is available in a 5 bump small bump micro SMD,
a 5 bump large bump micro SMD, a 5 bump thin micro SMD
and a 5 pin SOT-23 package. Performance is specified for
−40˚C to +125˚C temperature range and is available in 2.5V,
2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V. 3.1V, 3.2V, 3.3V, 4.7V,
4.8V and 5.0V output voltages. For other output voltage
options between 2.5V to 5.0V or for a dual LP3985, please
contact National Semiconductor sales office.
Key Specifications
n 2.5 to 6.0V input range
n 150mA guaranteed output
n 50dB PSRR at 1kHz @ VIN = VOUT + 0.2V
n 1.5µA quiescent current when shut down
n Fast Turn-On time: 200 µs (typ.)
n 100mV maximum dropout with 150mA load
n 30µVrms output noise (typ) over 10Hz to 100kHz
n −40 to +125˚C junction temperature range for operation
n 2.5V, 2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V, 3.1V, 3.2V,
3.3V, 4.7V, 4.8V and 5.0V outputs standard
Features
n Miniature 5-I/O micro SMD and SOT-23-5 package
n Logic controlled enable
n Stable with ceramic and high quality tantalum capacitors
n Fast turn-on
n Thermal shutdown and short-circuit current limit
Applications
n CDMA cellular handsets
n Wideband CDMA cellular handsets
n GSM cellular handsets
n Portable information appliances
Typical Application Circuit
Note: Pin Numbers in parenthesis indicate micro SMD package.
* Optional Noise Reduction Capacitor.
10136402
© 2003 National Semiconductor Corporation DS101364
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LP3985IBL-2.5 Datasheet, Funktion
Electrical Characteristics (Continued)
Unless otherwise specified: VIN = VOUT(nom) + 0.5V, CIN = 1 µF, IOUT = 1mA, COUT = 1 µF, CBYPASS = 0.01µF. Typical values
and limits appearing in standard typeface are for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, −40˚C to +125˚C. (Note 7) (Note 8)
Symbol
Parameter
Conditions
Limit
Typ Units
Min Max
TON Turn-On Time
(Note 11)
CBYPASS = 0.01 µF
200
µs
en Output Noise Voltage(Note 12) BW = 10 Hz to 100 kHz,
COUT = 1µF
Output Noise Density
CBP = 0
30
230
µVrms
nV/
IEN
VIL
VIH
COUT
TSD
Maximum Input Current at EN
Maximum Low Level Input
Voltage at EN
Minimum High Level Input
Voltage at EN
Output Capacitor
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
VEN = 0.4 and VIN = 6.0
VIN = 2.5 to 6.0V
VIN = 2.5 to 6.0V
Capacitance
ESR
±1 nA
0.4 V
1.4 V
1 20 µF
5 500 m
160 ˚C
20 ˚C
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical
Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: Additional information on lead temperature and pad temperature can be found in National Semiconductor Application Note (AN-1112).
Note 4: The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula: PD = (TJ - TA)/θJA,
where TJ is the junction temperature, TA is the ambient temperature, and θ JA is the junction-to-ambient thermal resistance. The 364mW rating for SOT23-5
appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction temperature, 150˚C, for TJ, 70˚C for TA, and 220˚C/W for θJA.
More power can be dissipated safely at ambient temperatures below 70˚C . Less power can be dissipated safely at ambient temperatures above 70˚C. The Absolute
Maximum power dissipation can be increased by 4.5mW for each degree below 70˚C, and it must be derated by 4.5mW for each degree above 70˚C.
Note 5: The human body model is 100pF discharged through 1.5kresistor into each pin. The machine model is a 200 pF capacitor discharged directly into each
pin.
Note 6: Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The 250mW rating for
SOT23-5 appearing under Operating Ratings results from substituting the maximum junction temperature for operation, 125˚C, for TJ, 70˚C for TA, and 220˚C/W for
θJA into (Note 4) above. More power can be dissipated at ambient temperatures below 70˚C . Less power can be dissipated at ambient temperatures above 70˚C.
The maximum power dissipation for operation can be increased by 4.5mW for each degree below 70˚C, and it must be derated by 4.5mW for each degree above
70˚C.
Note 7: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TJ = 25˚C or correlated using
Statistical Quality Control (SQC) methods. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations
and applying statistical process control.
Note 8: The target output voltage, which is labeled VOUT(nom), is the desired voltage option.
Note 9: An increase in the load current results in a slight decrease in the output voltage and vice versa.
Note 10: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply
for input voltages below 2.5V.
Note 11: Turn-on time is time measured between the enable input just exceeding VIH and the output voltage just reaching 95% of its nominal value.
Note 12: The output noise varies with output voltage option. The 30µVrms is measured with 2.5V voltage option. To calculate an approximated output noise for other
options, use the equation: (30µVrms)(X)/2.5, where X is the voltage option value.
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10136408
FIGURE 1. Line Transient Input Test Signal
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LP3985IBL-2.5 pdf, datenblatt
Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1 µF Ceramic,
CBYPASS = 0.01 µF, VIN = VOUT + 0.2V, TA = 25˚C, Enable pin is tied to VIN. (Continued)
Load Transient Response (VIN = 3.2V)
Load Transient Response (VIN = 4.2V)
10136424
Enable Response (VIN = VOUT + 0.2V)
10136425
Enable Response (VIN = 4.2V)
10136453
Enable Response (VIN = VOUT + 0.2V)
10136454
Enable Response (VIN = 4.2V)
10136455
10136456
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