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Teilenummer | ADF5002 |
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Beschreibung | 4GHz to 18GHz Divide-by-8 Prescaler | |
Hersteller | Analog Devices | |
Logo | ||
Gesamt 12 Seiten FEATURES
Divide-by-8 prescaler
High frequency operation: 4 GHz to 18 GHz
Integrated RF decoupling capacitors
Low power consumption
Active mode: 30 mA
Power-down mode: 7 mA
Low phase noise: −153 dBc/Hz
Single dc supply: 3.3 V compatible with ADF4xxx PLLs
Temperature range: −40°C to +105°C
Small package: 3 mm × 3 mm LFCSP
APPLICATIONS
PLL frequency range extender
Point-to-point radios
VSAT radios
Communications test equipment
GENERAL DESCRIPTION
The ADF5002 prescaler is a low noise, low power, fixed RF
divider block that can be used to divide down frequencies as
high as 18 GHz to a lower frequency suitable for input to a
PLL IC, such as the ADF4156 or the ADF4106. The ADF5002
provides a divide-by-8 function. The ADF5002 operates from
a 3.3 V supply and has differential 100 Ω RF outputs to allow
direct interface to the differential RF inputs of PLLs such as
the ADF4156 and ADF4106.
4 GHz to 18 GHzwww.DataSheet4U.com
Divide-by-8 Prescaler
ADF5002
FUNCTIONAL BLOCK DIAGRAM
CE
RFIN
3pF
50Ω
BIAS
DIVIDE
BY 8
ADF5002
VDDx
100Ω
100Ω
1pF
1pF
RFOUT
RFOUT
GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
ADF5002
TYPICAL PERFORMANCE CHARACTERISTICS
0
–10
–20
–30
VDD = 3.0V
–40 VDD = 3.3V
VDD = 3.6V
–50
–60
0
5 10 15 20
INPUT FREQUENCY (GHz)
Figure 3. RF Input Sensitivity
25
30
www.DataSheet4U.com
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
2.4
FIRST HARMONIC
THIRD HARMONIC
FIFTH HARMONIC
SEVENTH HARMONIC
EIGHTH HARMONIC
NINTH HARMONIC
ELEVENTH HARMONIC
2.7 3.0 3.3
VDDx (V)
3.6
Figure 6. RF Output Harmonic Content vs. VDDx
40
IDD_IN
35 IDD_OUT
30
25
20
15
10
5 fIN = 10GHz, PIN = 0dBm
0
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9
VDDx (V)
Figure 4. IDD1 and IDD2 vs. VDDx, fIN = 10 GHz, PIN = 0 dBm
0
–1
–2 fIN = 10GHz, VDD = 3.3V
–3
–4
–5
–6
–7
–8
–9
–10
0
5 10 15 20 25
INPUT FREQUENCY (GHz)
30
Figure 7. RF Output Power vs. RF Input Frequency, fIN = 10 GHz, VDD = 3.3 V
0
–2
–4
–6
–8
–10
–12
–14
–16
–18 fIN = 10GHz, PIN = 0dBm
–20
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9
VDDx (V)
Figure 5. RF Output Power (Single-Ended) vs. VDDx, fIN = 10 GHz, PIN = 0 dBm
Rev. 0 | Page 6 of 12
6 Page ADF5002
NOTES
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©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08753-0-6/10(0)
Rev. 0 | Page 12 of 12
12 Page | ||
Seiten | Gesamt 12 Seiten | |
PDF Download | [ ADF5002 Schematic.PDF ] |
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