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PDF AD80066 Data sheet ( Hoja de datos )
| Número de pieza | AD80066 | |
| Descripción | Complete 16-Bit CCD/CIS Signal Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Complete 16-Bit
CCD/CIS Signal Processor
AD80066
FEATURES
GENERAL DESCRIPTION
16-bit, 24 MSPS analog-to-digital converter (ADC)
The AD80066 is a complete analog signal processor for imaging
4-channel operation up to 24 MHz (6 MHz/channel)
applications. It features a 4-channel architecture designed to sample
3-channel operation up to 24 MHz (8 MHz/channel)
and condition the outputs of linear charged coupled device (CCD)
Selectable input range: 3 V or 1.5 V peak-to-peak
or contact image sensor (CIS) arrays. Each channel consists of
Input clamp circuitry
an input clamp, correlated double sampler (CDS), offset digital-
Correlated double sampling
to-analog converter (DAC), and programmable gain amplifier
1×~6× programmable gain
(PGA), multiplexed to a high performance 16-bit ADC. For
±300 mV programmable offset
maximum flexibility, the AD80066 can be configured as a
Internal voltage reference
Multiplexed byte-wide output
Optional single-byte output mode
3-wire serial digital interface
3 V/5 V digital I/O compatibility
Power dissipation: 490 mW at 24 MHz operation
Reduced power mode and sleep mode available
28-lead SSOP package
APPLICATIONS
4-channel, 3-channel, 2-channel, or 1-channel device.
The CDS amplifiers can be disabled for use with sensors that
do not require CDS, such as CIS and CMOS sensors.
The 16-bit digital output is multiplexed into an 8-bit output word,
which is accessed using two read cycles. There is an optional
single-byte output mode. The internal registers are programmed
through a 3-wire serial interface and enable adjustment of the
gain, offset, and operating mode. The AD80066 operates from a
5 V power supply, typically consumes 490 mW of power, and is
Flatbed document scanners
packaged in a 28-lead SSOP.
Film scanners
Digital color copiers
Multifunction peripherals
FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS
CML
AVDD AVSS
CAPT CAPB
DRVDD DRVSS
VINA
CDS
9-BIT
DAC
PGA
BAND GAP
REFERENCE
AD80066
VINB
CDS
9-BIT
DAC
PGA
4:1
MUX
16-BIT 16 16:8 8
ADC
MUX
DOUT
(D[0:7])
VINC
VIND
OFFSET
CDS
9-BIT
DAC
CDS
9-BIT
DAC
INPUT
CLAMP
BIAS
PGA
CONFIGURATION
REGISTER
PGA
9
MUX
REGISTER
6
CH. A
CH. B
CH. C
CH. D
CH. A
CH. B
CH. C
CH. D
GAIN
REGISTERS
OFFSET
REGISTERS
DIGITAL
CONTROL
INTERFACE
SCLK
SLOAD
SDATA
CDSCLK1 CDSCLK2
Figure 1.
ADCCLK
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD80066
Data Sheet
Parameter
POWER DISSIPATION
4-Channel Mode at 24 MHz
1-Channel Mode at 12 MHz
4-Channel Mode at 8 MHz, Slow Power Mode3
Min Typ
490
300
165
Max Unit
mW
mW
mW
1 The linear input signal range is up to 3 V p-p when the CCD reference level is clamped to 3 V by the AD80066 input clamp (see Figure 2).
2 The PGA gain is approximately linear-in-dB but varies nonlinearly with register code (see the Programmable Gain Amplifiers (PGA) section for more information).
3 Measured with Bit D1 of the configuration register set high for 8 MHz, low power operation.
AVDD = 5V
2V TYP
RESET TRANSIENT
3V BIAS SET BY INPUT CLAMP
1.5V OR 3V p-p MAX INPUT SIGNAL RANGE
GND
Figure 2. Input Signal with the CCD Reference Level Clamped to 3 V
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 24 MHz, fCDSCLK1 = fCDSCLK2 = 6 MHz, CL = 10 pF, unless otherwise noted.
Table 2.
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS (DRVDD = 5 V)
High Level Output Voltage (IOH = 2 mA)
Low Level Output Voltage (IOL = 2 mA)
LOGIC OUTPUTS (DRVDD = 3 V)
High Level Output Voltage (IOH = 2 mA)
Low Level Output Voltage (IOL = 2 mA)
Symbol
VIH
VIL
IIH
IIL
CIN
VOH
VOL
VOH
VOL
Min Typ Max Unit
2.0
0.8
10
10
10
V
V
µA
µA
pF
4.5 V
0.5 V
2.5 V
0.5 V
Rev. B | Page 4 of 20
5 Page 
AD80066
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVDD 1
CDSCLK1 2
CDSCLK2 3
ADCCLK 4
DRVDD 5
DRVSS 6
(MSB) D7 7
D6 8
D5 9
D4 10
D3 11
D2 12
D1 13
(LSB) D0 14
AD80066
TOP VIEW
(Not to Scale)
28 AVSS
27 VINA
26 OFFSET
25 VINB
24 CML
23 VINC
22 CAPT
21 CAPB
20 VIND
19 AVSS
18 AVDD
17 SLOAD
16 SCLK
15 SDATA
Figure 13. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
1 AVDD
P
2
CDSCLK1
DI
3
CDSCLK2
DI
4
ADCCLK
DI
5
DRVDD
P
6 DRVSS P
7
D7 (MSB)
DO
8 D6
DO
9 D5
DO
10 D4
DO
11 D3
DO
12 D2
DO
13 D1
DO
14 D0 (LSB) DO
15 SDATA
DI/DO
16 SCLK
DI
17 SLOAD
DI
18 AVDD
P
19 AVSS
P
20 VIND
AI
21 CAPB
AO
22 CAPT
AO
23 VINC
AI
24 CML
AO
25 VINB
AI
26 OFFSET AO
27 VINA
AI
28 AVSS
P
Description
5 V Analog Supply.
CDS Reference Level Sampling Clock.
CDS Data Level Sampling Clock.
ADC Sampling Clock.
Digital Output Driver Supply (3 V or 5 V).
Digital Output Driver Ground.
Data Output MSB. ADC DB15 high byte; ADC DB7 low byte.
Data Output. ADC DB14 high byte; ADC DB6 low byte.
Data Output. ADC DB13 high byte; ADC DB5 low byte.
Data Output. ADC DB12 high byte; ADC DB4 low byte.
Data Output. ADC DB11 high byte; ADC DB3 low byte.
Data Output. ADC DB10 high byte; ADC DB2 low byte.
Data Output. ADC DB9 high byte; ADC DB1 low byte.
Data Output LSB. ADC DB8 high byte; ADC DB0 low byte.
Serial Interface Data Input/Output.
Serial Interface Clock Input.
Serial Interface Load Pulse.
5 V Analog Supply.
Analog Ground.
Analog Input, D Channel.
ADC Bottom Reference Voltage Decoupling.
ADC Top Reference Voltage Decoupling.
Analog Input, C Channel.
Internal Bias Level Decoupling.
Analog Input, B Channel.
Clamp Bias Level Decoupling.
Analog Input, A Channel.
Analog Ground.
1 AI = analog input, AO = analog output, DI = digital input, DO = digital output, and P = power.
Data Sheet
Rev. B | Page 10 of 20
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet AD80066.PDF ] | |
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