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H5DU1262GTR Schematic ( PDF Datasheet ) - Hynix Semiconductor

Teilenummer H5DU1262GTR
Beschreibung 128Mb DDR SDRAM
Hersteller Hynix Semiconductor
Logo Hynix Semiconductor Logo 




Gesamt 37 Seiten
H5DU1262GTR Datasheet, Funktion
www.DataSheet4U.com
128Mb DDR SDRAM
H5DU1262GTR
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0 / May 2009
1






H5DU1262GTR Datasheet, Funktion
PPrewww.DataSheet4U.com
H5DU1262GTR Series
Functinal Block Diagram (8M x16)
4Banks x 2Mbit x 16I/O Double Data Rate Syncronous DRAM
Write Data Register
2-RbMegiotidstePerrefetch Unit
32
16
DS
CLK
/CLK
CKE
/CS
/RAS
/CAS
/WE
LDM
UDM
A0
A1
Amax
BA0
BA1
Command
Decoder
Address
Buffer
Bank
Control
Mode
Register
Row
Decoder
2Mx16 BANK 3
2Mx16 BANK 2
2Mx16 BANK 1
2Mx16 BANK 0
Memory
Cell
Array
32
DQ0
16
DQ15
Column Address
Decoder
CLK,
/CLK
Column
Decoder
CLK_DLL
DLL
Block
LDQS,
UDQS
Data Strobe
Transmitter
Data Strobe
Receiver
LDQS,
UDQS
Mode
Register
Rev. 1.0 / May 2009
6

6 Page









H5DU1262GTR pdf, datenblatt
PPrewww.DataSheet4U.com
H5DU1262GTR Series
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is issued by the
low signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and
CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to
write the data in mode register. During the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until reset by another MRS command.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
00
Operating Mode
CAS Latency BT Burst Length
BA0 MRS Type
0 MRS
1 EMRS
A6 A5 A4 CAS Latency
00 0
Reserved
00 1
Reserved
01 0
2
01 1
3
10 0
4
10 1
1.5
11 0
2.5
11 1
Reserved
A12~A9 A8 A7 A6~A0
Operating Mode
0 0 0 Valid
Normal Operation
0 1 0 Valid Normal Operation/ Reset DLL
0
0 1 VS
Vendor specific Test Mode
-
--
-
All other states reserved
A3 Burst Type
0 Sequential
1 Interleave
Burst Length
A2 A1 A0
Sequential Interleave
000
Reserved
Reserved
001
2
2
010
4
4
011
8
8
100
Reserved
Reserved
101
Reserved
Reserved
110
Reserved
Reserved
111
Reserved
Reserved
Rev. 1.0 / May 2009
12

12 Page





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