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IMX51A Schematic ( PDF Datasheet ) - Freescale Semiconductor

Teilenummer IMX51A
Beschreibung i.MX51A Automotive and Infotainment Applications Processors
Hersteller Freescale Semiconductor
Logo Freescale Semiconductor Logo 




Gesamt 30 Seiten
IMX51A Datasheet, Funktion
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: IMX51AEC
Rev. 6, 10/2012
IMX51A
i.MX51A Automotive and
Infotainment Applications
Processors
Package Information
Plastic Package
Case 2017 19 x 19 mm, 0.8 mm pitch
Ordering Information
See Table 1 on page 2 for ordering information.
1 Introduction
The MCIMX51A (i.MX51A) Automotive Infotainment
Processor represents Freescale Semiconductor’s latest
addition to a growing family of multimedia focused
products offering high performance processing with a
high degree of functional integration, aimed at the
growing automotive infotainment market. This device
includes two graphics processors, 720p video
processing, dual display, and many I/Os.
The i.MX51A processor features Freescale’s advanced
implementation of the ARM Cortex A8™ core, targeting
speeds up to 600 MHz with 200 MHz I/O bus clock
DDR2 and mobile DDR. This device is well-suited for
graphics rendering for HMI and navigation, high
performance speech processing with large databases,
video processing and display, audio playback and
ripping, and many other applications.
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 2
1.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1. Special Signal Considerations . . . . . . . . . . . . . . . 11
3. IOMUX Configuration for Boot Media . . . . . . . . . . . . . . . 13
3.1. NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2. SD/MMC IOMUX Pin Configuration . . . . . . . . . . . 14
3.3. I2C IOMUX Pin Configuration . . . . . . . . . . . . . . . . 14
3.4. eCSPI/CSPI IOMUX Pin Configuration . . . . . . . . 15
3.5. Wireless External Interface Module (WEIM) . . . . 15
3.6. UART IOMUX Pin Configuration . . . . . . . . . . . . . 15
3.7. USB-OTG IOMUX Pin Configuration . . . . . . . . . . 15
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 16
4.2. Supply Power-Up/Power-Down Requirements and
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4. Output Buffer Impedance Characteristics . . . . . . 29
4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 33
4.6. Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.7. External Peripheral Interfaces . . . . . . . . . . . . . . . 72
5. Package Information and Contact Assignments . . . . . 151
5.1. 19 x 19 mm Package Information . . . . . . . . . . . . 151
5.2. 19 x 19 mm, 0.8 Pitch Ball Map . . . . . . . . . . . . . 169
6. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
© 2012 Freescale Semiconductor, Inc. All rights reserved.






IMX51A Datasheet, Funktion
Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block
Mnemonic
Block Name Subsystem
Brief Description
eSDHC-4
(muxed with
P-ATA)
Enhanced
Multi-Media
Card/
Secure Digital
Host
Controller
Connectivity
Peripherals
Can be configured as eSDHC (see above) and is muxed with the P-ATA
interface.
FEC
FIRI
GPIO-1
GPIO-2
GPIO-3
GPIO-4
GPT
GPU
GPU2D
I2C-1
I2C-2
HS-I2C
Fast Ethernet Connectivity
Controller
Peripherals
Fast
Infra-Red
Interface
General
Purpose I/O
Modules
Connectivity
Peripherals
System
Control
Peripherals
The Ethernet Media Access Controller (MAC) is designed to support both
10 Mbps and 100 Mbps ethernet/IEEE Std 802.3™ networks. An external
transceiver interface and transceiver function are required to complete the
interface to the media.
Fast Infra-Red Interface
These modules are used for general purpose input/output to external ICs. Each
GPIO module supports up to 32 bits of I/O.
General
Purpose
Timer
Timer
Peripherals
Graphics
Processing
Unit
Multimedia
Peripherals
Graphics
Multimedia
Processing Peripherals
Unit-2D Ver. 1
I2C Interface Connectivity
Peripherals
Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a
programmable prescaler and compare and capture register. A timer counter
value can be captured using an external event, and can be configured to trigger
a capture event on either the leading or trailing edges of an input pulse. When
the timer is configured to operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with minimal processor
intervention. The counter has output compare logic to provide the status and
interrupt at comparison. This timer can be configured to run either on an external
clock or on an internal clock.
The GPU provides hardware acceleration for 2D and 3D graphics
algorithms with sufficient processor power to run desk-top quality
interactive graphics applications on displays up to HD720
resolution. It supports color representation up to 32 bits per pixel.
The GPU with its 128 KByte memory enables high performance mobile 3D and
2D vector graphics at rates up to 27 Mtriangles/sec, 166 Mpixels/sec,
664 Mpixels/sec (Z).
The GPU2D provides hardware acceleration for 2D graphic
algorithms with sufficient processor power to run desk-top quality
interactive graphics applications on displays up to HD720 resolution.
I2C provides serial interface for controlling peripheral devices. Data rates of up
to 400 Kbps are supported by two of the I2C ports. Data rates of up to 3.4 Mbps
(I2C Specification v2.1) are supported by the HS-I2C.
Note: See the errata for the HS-I2C in the i.MX51 Chip Errata. The two standard
I2C modules have no errata.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
6 Freescale Semiconductor

6 Page









IMX51A pdf, datenblatt
Features
Table 3. Special Signal Considerations (continued)
Signal Name
Remarks
GPIO_NAND
IOB, IOG, IOR,
IOB_BACK, IOG_BACK,
and IOR_BACK
JTAG_nnnn
NC
PMIC_INT_REQ
POR_B
RESET_IN_B
RREFEXT
SGND, SVCC, and
SVDDGP
STR
TEST_MODE
This is a general-purpose input/output (GPIO3_12) on the NVCC_NANDF_A power rail.
These signals are analog TV outputs that should be tied to GND when not being used.
The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,
if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is
followed. For example, do not use an external pull down on an input that has on-chip pull-up.
JTAG_TDO is configured with a keeper circuit such that the floating condition is eliminated if an
external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and
should be avoided.
JTAG_MOD is referenced as SJC_MOD in the i.MX51 Multimedia Applications Processor
Reference Manual (MCIMX51RM). Both names refer to the same signal. JTAG_MOD must be
externally connected to GND for normal operation. Termination to GND through an external
pull-down resistor (such as 1 kΩ) is allowed.
These signals are No Connect (NC) and should be floated by the user.
When using the MC13892 power management IC, the PMIC_INT_REQ high-priority interrupt input
on i.MX51 should be either floated or tied to NVCC_SRTC_POW with a 4.7 kΩ to 68 kΩ resistor.
This avoids a continuous current drain on the real-time clock backup battery due to a 100 kΩ
on-chip pull-up resistor.
PMIC_INT_REQ is not used by the Freescale BSP (board support package) software. The BSP
requires that the general-purpose INT output from the MC13892 be connected to the i.MX51 GPIO
input GPIO1_8 configured to cause an interrupt that is not high-priority.
The original intent was for PMIC_INT_REQ to be connected to a circuit that detects when the
battery is almost depleted. In this case, the I/O must be configured as alternate mode 0 (ALT0 =
power fail).
This cold reset negative logic input resets all modules and logic in the IC.
Note: The POR_B input must be immediately asserted at power-up and remain asserted until
after the last power rail is at its working voltage.
This warm reset negative logic input resets all modules and logic except for the following:
• Test logic (JTAG, IOMUXC, DAP)
• SRTC
• Memory repair – Configuration of memory repair per fuse settings
• Cold reset logic of WDOG – Some WDOG logic is only reset by POR_B. See WDOG chapter
in i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM) for details.
Determines the reference current for the USB PHY bandgap reference. An external 6.04 kΩ 1%
resistor to GND is required.
These sense lines provide the ability to sense actual on-chip voltage levels on their respective
supplies. SGND monitors differentials of the on-chip ground versus an external power source.
SVCC monitors on-chip VCC, and SVDDGP monitors VDDGP. Freescale recommends connection
of the SVCC and SVDDGP signals to the feedback inputs of switching power-supplies or to test
points.
This signal is reserved for Freescale manufacturing use. The user should float this signal.
TEST_MODE is for Freescale factory use only. This signal is internally connected to an on-chip
pull-down device. Users must either float this signal or tie it to GND.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
12 Freescale Semiconductor

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