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PDF HT45B0K Data sheet ( Hoja de datos )
| Número de pieza | HT45B0K | |
| Descripción | SPI to USB Bridge | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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HT45B0K
SPI to USB Bridge
www.DataSheet4U.com
Features
● Glueless slave SPI interface to Holtek's MCU
● USB (Universal Serial Bus) 1.1 Full-speed module
− 6 endpoints (endpoint 0 included)
− FIFO: 8, 8, 8, 64, 8, 64 for EP0~EP5 respectively
● Operating voltage: VDD = 3.3V~5.5V
● 6MHz/12MHz (CLKI) external clock input for USB PLL clock
● Suspend Mode with low suspend current
● Remote Wake-up function
● USB Multiple Interrupt Generation Sources:
♦ Access of the corresponding USB FIFO from the USB host
♦ USB suspend signal from the USB host
♦ USB resume signal from the USB host
♦ USB Reset signal from the USB host
● CMOS external clock input, CLKI, with frequency 6MHz/12MHz for the USB PLL clock
● 16-pin NSOP package
General Description
This device is a companion chip for microcontrollers to provide USB connectivity with the USB
host. Six USB endpoints are supported with 8/8/8/64/8/64-byte FIFO for endpoint 0~5 respectively.
An external interrupt output to the host MCU is used for inetrrupt-driven operation.
However, the host MCU may also poll the status register to obtain the latest status if the interrupt is
not used.
The possible applications include low-cost data links for computers/peripherals, portable and
battery operated devices/instruments, factory automation and process control.
Block Diagram
SDI
SDO
SCK
S e r ia l
I/O
V D D In te rfa c e
USB
M o d u le
V 33O
UDP
UDN
SCS
C LK I
P LL 48M H z
IN T
V D D T o a ll
c h ip
G N D pow er
Rev 1.00 1 March 22, 2010
1 page  
HT45B0K
SPI to USB Bridge
www.DataSheet4U.com
Functional Description
SPI Interface
The MCU communicates with the USB Module via an internal SPI interface. The SPI interface
on this device is comprised of four signals: (SPI Chip Select), SCK (SPI Clock), SDI (Serial
Data Input) and SDO (Serial Data Output). The SPI master, which is the MCU, asserts by
pulling it low to start the data transaction cycle. When the first 8 bits of data are transmitted,
should not return to a high level. Instead, must remain at a low level until the whole 16-bit
data transaction is completed. If is de-asserted, that is returned to a high level, before the 16-
bit data transaction is completed, all data bits will be discarded by the USB Module SPI slave.
SPI Timing
Both read and write operations are conducted along the SPI common interface with the following
format:
● Write Type Format: 8-bit command input + 8-bit data input
● Read Type Format: 8-bit command input + 8-bit data output
To initiate a data transaction, the MCU master SPI needs to pull to a low level first and then
also pull SCK low. The input data bit on SDI should be stable before the next SCK rising edge,
as the device will latch the SDI status on the next SCK rising edge. Regarding the SDO line, the
output data bit will be updated on the SCK falling edge. The master needs to obtain the line status
before the next SCK falling edge.
There are 16 bits of data transmitted and/or received by the SPI interface for each transaction. Each
transaction consists of a command phase and a data phase. When is high, the SPI interface is
disabled and SDO will be set to a high impedance state.
After a complete transaction has been implemented, which requires 16 SCK clock cycles, the
master needs to set to a high level in preparation for the next data transaction.
For write operations, the device will begin to execute the command only after it receives a 16-bit
serial data sequence and when the has been set high again by the master.
For read operations, the device will begin to execute the command only after it receives an 8-bit
read command after which it will be ready to output data. If necessary, the master can de-assert
the pin to abort the transaction at any time which will cause any data transactions to be
abandoned.
Commands and Registers
There are 2 types of commands:
● Read Register
● Write Register
Command/Address Format
Command Type
Read Register
Write Register
Bit.7
0
1
Bit.6
X
X
Bit.5
X
X
Bit.4
A4
A4
Bit.3
A3
A3
Bit.2
A2
A2
Bit.1
A1
A1
Bit.0
A0
A0
There are 17 registers available to control the USB module which are addressed by 5 address bits
A4~ A0 of Read /Write Register commands.
Rev 1.00 5 March 22, 2010
5 Page 
HT45B0K
SPI to USB Bridge
www.DataSheet4U.com
AWR Register
The AWR register contains the USB device address and the Remote wake-up function control bit.
The initial value of the USB device address is 00H. The address value extracted from the USB
command is to be immediately loaded into this register or not depending upon the device address
update control bit ASET in the SIES register.
AWR Register
Bit
Name
R/W
POR
7654 3 21
UAD6 UAD5 UAD4 UAD3
UAD2
UAD1 UAD0
R/W R/W R/W R/W R/W R/W R/W
0000 0 00
Bit 7~1 UAD6~UAD0: USB device address
Bit 0 WKEN: USB device Remote Wake-up function enable control
0: disable USB remote wake-up function
1: enable USB remote wake-up function
0
WKEN
R/W
0
STALL Register
The STALL register shows whether the corresponding endpoint works properly or not. As soon
as the endpoint works improperly, the related bit in the STALL register has to be set to 1 by
application program. The contents of the STALL register will be cleared by USB reset signal.
STALL Register
Bit
Name
R/W
POR
7
―
―
―
Bit 7~6
Bit 5~0
654 3 210
―
STL5
STL4
STL3
STL2
STL1
STL0
― R/W R/W R/W R/W R/W R/W
―1
1
1
11
1
Unimplemented, read as “0”.
STL5~STL0: USB endpoint stall indication
0: the corresponding USB endpoint is not stalled.
1: the corresponding USB endpoint is stalled.
The STL bit is set by users when the related USB endpoint is stalled. These
bits are cleared by USB reset signal. For endpoint 0 the stall bit STL0 can also
be cleared by Setup Token event.
Rev 1.00 11 March 22, 2010
11 Page | ||
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| PDF Descargar | [ Datasheet HT45B0K.PDF ] | |
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