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AD9148 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9148
Beschreibung TxDAC+ Digital-to-Analog Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9148 Datasheet, Funktion
Data Sheet
Quad 16-Bit,1 GSPS,
TxDAC+ Digital-to-Analog Converter
AD9148
FEATURES
Single-carrier W-CDMA ACLR = 80 dBc at 150 MHz IF
Channel-to-channel isolation > 90 dB
Analog output
Adjustable 8.7 mA to 31.7 mA
RL = 25 Ω to 50 Ω
Novel 2×, 4×, and 8× interpolator eases data interface
On-chip fine complex NCO allows carrier placement
anywhere in DAC bandwidth
High performance, low noise PLL clock multiplier
Multiple chip synchronization interface
Programmable digital inverse sinc filter
Auxiliary DACs allow for offset control
Gain DACs allow for I and Q gain matching
Programmable I and Q phase compensation
Digital gain control
Flexible LVDS digital I/F supports 32- or 16-bit bus width
196-ball CSP_BGA, 12 mm × 12 mm
APPLICATIONS
Wireless infrastructure
LTE, TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM
MIMO/transmit diversity
Digital high or low IF synthesis
GENERAL DESCRIPTION
The AD9148 is a quad, 16-bit, high dynamic range, digital-to-
analog converter (DAC) that provides a sample rate of 1000 MSPS.
This device includes features optimized for direct conversion
transmit applications, including gain, phase, and offset compen-
sation. The DAC outputs are optimized to interface seamlessly with
analog quadrature modulators such as the ADL5371/ADL5372/
ADL5373/ADL5374/ADL5375. A serial peripheral interface (SPI)
is provided for programming of the internal device parameters.
Full-scale output current can be programmed over a range of 8.7 mA
to 31.7 mA. The device operates from 1.8 V and 3.3 V supplies
for a total power consumption of 3 W at the maximum sample
rate. The AD9148 is enclosed in a 196-ball chip scale package ball
grid array with the option of an attached heat spreader.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) enable
high quality synthesis of wideband signals from baseband
to high intermediate frequencies.
2. A proprietary DAC output switching technique enhances
dynamic performance.
3. The current outputs are easily configured for various
single-ended or differential circuit topologies.
4. The LVDS data input interface includes FIFO to ease input
timing.
COMPLEX BASEBAND
TYPICAL SIGNAL CHAIN
COMPLEX IF
RF
DC
FPGA/ASIC/DSP
fIF
DIGITAL INTERPOLATION FILTERS
↑2 ↑2 ↑2
DAC1
↑2 ↑2 ↑2
DAC2
LO ± fIF
POST DAC
ANALOG FILTER
AQM
LO
PA
↑2 ↑2 ↑2
DAC3
↑2 ↑2 ↑2
DAC4
POST DAC
LO
AQM
PA
NOTES
1. AQM = ANALOG QUADRATURE MODULATOR.
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.






AD9148 Datasheet, Funktion
Data Sheet
AD9148
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 1.
Parameter
Min Typ
Max Unit
RESOLUTION
16 Bits
ACCURACY
Differential Nonlinearity (DNL)
±2.1 LSB
Integral Nonlinearity (INL)
±3.7 LSB
MAIN DAC OUTPUTS
Offset Error
±0.001
% FSR
Gain Error (with Internal Reference)
±2 % FSR
Full-Scale Output Current1
8.66 20.2
31.66
mA
Output Compliance Range
−1.0 +1.0 V
Output Resistance
10 MΩ
Gain DAC Monotonicity
Guaranteed
Settling Time to Within ±0.5 LSB
20 ns
TEMPERATURE DRIFT
Main DAC Offset
0.04 ppm/°C
Main DAC Gain
100 ppm/°C
Reference Voltage
30 ppm/°C
REFERENCE
Internal Reference Voltage
1.2 V
Output Resistance
5 kΩ
ANALOG SUPPLY VOLTAGES
AVDD33
3.13 3.3
3.47 V
CVDD18
1.71 1.8
1.89 V
DIGITAL SUPPLY VOLTAGES
IOVDD
1.71
1.8/3.3
3.47 V
DVDD18
1.71 1.8
1.89 V
POWER CONSUMPTION (NCO OFF, PLL DISABLED, AND SINC−1 FILTER BYPASSED,
UNLESS OTHERWISE NOTED)
1 × Mode, fDAC = 300 MSPS, fINTERFACE = 600 MSPS
0.79 W
2 × Mode, fDAC = 500 MSPS, fINTERFACE = 500 MSPS
1.49 W
4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS
2.18 W
4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS, NCO On
2.47 W
4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS, PLL Enabled
2.26 W
4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS, Sinc−1 Filter Enabled
2.44 W
8 × Mode, fDAC = 800 MSPS, fINTERFACE = 200 MSPS
2.01 2.16 W
AVDD33
368 373 mW
CVDD18
261 280 mW
IOVDD
0.8 1.6 mW
DVDD18
1377
1504
mW
Power-Down Mode
1 12 mW
OPERATING RANGE
−40 +25
+85 °C
1 Based on a 10 kΩ external resistor.
Rev. B | Page 5 of 72

6 Page









AD9148 pdf, datenblatt
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
A
2345
IOUT2 IOUT2
6
CLK
78
VREF I120
9
REF
10 11 12 13
IOUT3 IOUT3
14
A
B
AUX2 AUX2
CLK NC NC REF
AUX3 AUX3
B
C IOUT1 AUX1
D IOUT1 AUX1
AUX4 IOUT4 C
AUX4 IOUT4 D
E ++++ E
F XXXXXX
F
GG
HH
JJ
KK
LL
MM
NN
PP
1 2 3 4 5 6 7 8 9 10 11 12 13 14
+ CVDD18
X AVDD33
AVSS
CLK
POSITIVE
TERMINAL
CLK
NEGATIVE
TERMINAL
Figure 4. Pin Configuration (Top View), Analog and Clock Domain Pins
AD9148
Rev. B | Page 11 of 72

12 Page





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