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PDF ADRF6601 Data sheet ( Hoja de datos )
| Número de pieza | ADRF6601 | |
| Descripción | 300 MHz to 2500 MHz Rx Mixer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
300 MHz to 2500 MHz Rx Mixer with
Integrated Fractional-N PLL and VCO
ADRF6601
FEATURES
Rx mixer with integrated fractional-N PLL
RF input frequency range: 300 MHz to 2500 MHz
Internal LO frequency range: 750 MHz to 1160 MHz
Input P1dB: 14.5 dBm
Input IP3: 31 dBm
IIP3 optimization via external pin
SSB noise figure
IP3SET pin open: 13.5 dB
IP3SET pin at 3.3 V: 14.6 dB
Voltage conversion gain: 6.7 dB
Matched 200 Ω IF output impedance
IF 3 dB bandwidth: 500 MHz
Programmable via 3-wire SPI interface
40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
Cellular base stations
GENERAL DESCRIPTION
The ADRF6601 is a high dynamic range active mixer with an
integrated phase-locked loop (PLL) and a voltage controlled
oscillator (VCO). The PLL/synthesizer uses a fractional-N
PLL to generate a fLO input to the mixer. The reference input
can be divided or multiplied and then applied to the PLL phase
frequency detector (PFD).
The PLL can support input reference frequencies from 12 MHz
to 160 MHz. The PFD output controls a charge pump whose
output drives an off-chip loop filter.
The loop filter output is then applied to an integrated VCO. The
VCO output at 2 × fLO is applied to an LO divider, as well as to a
programmable PLL divider. The programmable PLL divider is
controlled by a sigma-delta (Σ-Δ) modulator (SDM). The modulus
of the SDM can be programmed from 1 to 2047.
The active mixer converts the single-ended 50 Ω RF input to
a 200 Ω differential IF output. The IF output can operate up
to 500 MHz.
The ADRF6601 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, RoHS-compliant,
6 mm × 6 mm LFCSP with an exposed paddle. Performance is
specified over the −40°C to +85°C temperature range.
Table 1.
Part No.
ADRF6601
ADRF6602
ADRF6603
ADRF6604
Internal LO
Range
750 MHz
1160 MHz
1550 MHz
2150 MHz
2100 MHz
2600 MHz
2500 MHz
2900 MHz
±3 dB RFIN
Balun Range
300 MHz
2500 MHz
1000 MHz
3100 MHz
1100 MHz
3200 MHz
1200 MHz
3600 MHz
±1 dB RFIN
Balun Range
450 MHz
1600 MHz
1350 MHz
2750 MHz
1450 MHz
2850 MHz
1600 MHz
3200 MHz
LODRV_EN 36
LON 37
LOP 38
PLL_EN 16
DATA 12
CLK 13
LE 14
REF_IN 6
MUXOUT 8
FUNCTIONAL BLOCK DIAGRAM
VCC1
1
VCC2
10
VCC_LO
17
VCC_MIX VCC_V2I
22 27
VCC_LO
34
NC NC
32 33
ADRF6601
INTERNAL LO RANGE
750MHz TO 1160MHz
3.3V
LDO
BUFFER
2.5V
LDO
2 DECL3P3
9 DECL2P5
SPI
INTERFACE
×2
MUX
÷2
÷4
FRACTION
REG
MODULUS
INTEGER
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
21 TO 123
TEMP
SENSOR
–
+
PHASE
FREQUENCY
DETECTOR
BUFFER
PRESCALER
÷2
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
2:1
MUX
DIV
BY
4, 2, 1
VCO
CORE
VCO
LDO
40 DECLVCO
26 RFIN
29 IP3SET
4 7 11 15 20 21 23 24 25 28 30 31 35
GND
5
RSET
3 39
18 19
CP VTUNE IFP IFN
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
TIMING CHARACTERISTICS
VS = 5 V ± 5%.
Table 5.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Timing Diagram
CLK
DATA
LE
DB23 (MSB)
t1
t2 t3
DB22
Description
LE setup time
DATA-to-CLK setup time
DATA-to-CLK hold time
CLK high duration
CLK low duration
CLK-to-LE setup time
LE pulse width
t4 t5
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
Figure 2. Timing Diagram
ADRF6601
DB0 (LSB)
(CONTROL BIT C1)
t6 t7
Rev. B | Page 5 of 32
5 Page 
Data Sheet
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
750
IP3SET = OPEN
IP3SET = 3.3V
TA = +85°C
TA = +25°C
TA = –40°C
800 850 900 950 1000 1050 1100 1150
LO FREQUENCY (MHz)
Figure 14. LO-to-IF Feedthrough vs. LO Frequency,
LO Output Turned Off, CDAC = 0x0
–30
IP3SET = OPEN
IP3SET = 3.3V
–40
TA = +85°C
TA = +25°C
TA = –40°C
–50
–60
–70
–80
–90
750 800 850 900 950 1000 1050 1100 1150
LO FREQUENCY (MHz)
Figure 15. LO-to-RF Leakage vs. LO Frequency, LO Output Turned Off
0
–5
–10
–15
–20
–25
–30
–35
–40
500 600 700 800 900 1000 1100 1200 1300
RF FREQUENCY (MHz)
Figure 16. RF Input Return Loss vs. RF Frequency
ADRF6601
0
–5
–10
–15
–20
–25
–30
–35
–40
500 600 700 800 900 1000 1100 1200 1300
LO FREQUENCY (MHz)
Figure 17. LO Input Return Loss vs. LO Frequency (Including TC1-1-13 Balun)
350 3.5
300
RESISTANCE
250
3.0
2.5
200 2.0
150
CAPACITANCE
100
1.5
1.0
50 0.5
00
50 100 150 200 250 300 350 400 450 500
IF FREQUENCY (MHz)
Figure 18. IF Differential Output Impedance (R Parallel C Equivalent)
35
IP3SET = OPEN
IP3SET = 3.3V
30
25
20
15
10
–60
–50 –40 –30 –20 –10
CW BLOCKER LEVEL (dBm)
0
Figure 19. SSB Noise Figure vs. 5 MHz Offset Blocker Level,
LO Frequency = 1055 MHz, RF Frequency = 915 MHz
Rev. B | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADRF6601.PDF ] | |
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