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ADF4158 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADF4158
Beschreibung Direct Modulation/Waveform Generating 6.1 GHz Fractional-N Frequency Synthesizer
Hersteller Analog Devices
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Gesamt 30 Seiten
ADF4158 Datasheet, Funktion
Data Sheet
Direct Modulation/Waveform Generating,
6.1 GHz Fractional-N Frequency Synthesizer
ADF4158
FEATURES
GENERAL DESCRIPTION
Radio frequency (RF) bandwidth to 6.1 GHz
25-bit fixed modulus allows subhertz frequency resolution
Frequency and phase modulation capability
Sawtooth and triangular waveforms in the frequency domain
Parabolic ramp
Ramp superimposed with FSK
Ramp with 2 different sweep rates
Ramp delay
Ramp frequency readback
Ramp interruption
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Cycle slip reduction for faster lock times
Switched bandwidth fast-lock mode
Qualified for automotive applications
APPLICATIONS
The ADF4158 is a 6.1 GHz fractional-N frequency synthesizer
with direct modulation and waveform generation capability. It
contains a 25-bit fixed modulus, allowing subhertz resolution at
6.1 GHz. It consists of a low noise digital phase frequency
detector (PFD), a precision charge pump, and a programmable
reference divider. There is a sigma-delta (Σ-Δ) based fractional
interpolator to allow programmable fractional-N division. The
INT and FRAC registers define an overall N-divider as N = INT +
(FRAC/225).
The ADF4158 can be used to implement frequency shift keying
(FSK) and phase shift keying (PSK) modulation. There are also
a number of frequency sweep modes available that generate
various waveforms in the frequency domain, for example,
sawtooth and triangular waveforms. The ADF4158 features
cycle slip reduction circuitry, which leads to faster lock times,
without the need for modifications to the loop filter.
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
Frequency modulated continuous wave (FMCW) radar
Communications test equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP
RSET
ADF4158
REFIN
MUXOUT
CE
TXDATA
×2
DOUBLER
5-BIT
R-COUNTER
÷2
DIVIDER
HIGH-Z
OUTPUT
MUX
VDD
DGND
VDD
RDIV
NDIV
LOCK
DETECT
+ PHASE
FREQUENCY
DETECTOR
REFERENCE
CHARGE
PUMP
CSR
FLO SWITCH
N-COUNTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
SW2
CP
SW1
RFINA
RFINB
CLK
DATA
LE
32-BIT
DATA
REGISTER
FRACTION MODULUS
REG
225
INTEGER
REG
AGND
DGND
Figure 1.
CPGND
Rev. G
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Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved.
Technical Support
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ADF4158 Datasheet, Funktion
ADF4158
Table 3. Read Timing
Parameter
Limit at TMIN to TMAX (C Version)
t1 20
t2 20
t3 25
t4 25
t5 10
Read Timing Diagram
TXDATA
t1
CLK
MUXOUT
DB36
t2
DB35
Unit
ns min
ns min
ns min
ns min
ns min
t3 t4
DB2
DB1
LE
NOTES
1. LE SHOULD BE KEPT HIGH DURING READBACK.
Figure 3. Read Timing Diagram
Data Sheet
Test Conditions/Comments
TXDATA setup time
CLK setup time to DATA (on MUXOUT)
CLK high duration
CLK low duration
CLK to LE setup time
DB0
t5
100µA IOL
TO OUTPUT
PIN CL
10pF
1.5V
100µA IOH
Figure 4. Load Circuit for MUXOUT Timing, CL = 10 pF
Rev. G | Page 6 of 36

6 Page









ADF4158 pdf, datenblatt
ADF4158
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R-counter and N-counter and
produces an output proportional to the phase and frequency
difference between them. Figure 19 shows a simplified schematic
of the PFD. The PFD includes a fixed delay element that sets the
width of the antibacklash pulse, which is typically 3 ns. This pulse
ensures that there is no dead zone in the PFD transfer function
and gives a consistent reference spur level.
HIGH
UP
D1 Q1
U1
+IN CLR1
DELAY U3
CHARGE
PUMP
CP
HIGH
–IN
CLR2 DOWN
D2 Q2
U2
Figure 19. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4158 allows the user to access
various internal points on the chip. The state of MUXOUT is
controlled by the M4, M3, M2, and M1 bits (see Figure 23).
Figure 20 shows the MUXOUT section in block diagram form.
THREE-STATE OUTPUT
DVDD
DGND
R-DIVIDER OUTPUT
N-DIVIDER OUTPUT
DIGITAL LOCK DETECT
SERIAL DATA OUTPUT
MUX
CONTROL
CLK DIVIDER OUTPUT
R-DIVIDER/2
N-DIVIDER/2
FAST-LOCK SWITCH
READBACK TO MUXOUT
Figure 20. MUXOUT Schematic
DVDD
MUXOUT
DGND
Data Sheet
INPUT SHIFT REGISTERS
The ADF4158 digital section includes a 5-bit RF R-counter, a
12-bit RF N-counter, and a 25-bit FRAC counter. Data is clocked
into the 32-bit shift register on each rising edge of CLK. The
data is clocked in MSB first. Data is transferred from the shift
register to one of eight latches on the rising edge of LE. The
destination latch is determined by the state of the three control
bits (C3, C2, and C1) in the shift register. These are the three
LSBs—DB2, DB1, and DB0—as shown in Figure 2. The truth
table for these bits is shown in Table 6. Figure 21 and Figure 22
show a summary of how the latches are programmed.
PROGRAM MODES
Table 6 and Figure 23 through Figure 30 show how to set up the
program modes in the ADF4158.
Several settings in the ADF4158 are double buffered. These include
the LSB fractional value, R-counter value, reference doubler,
current setting, and RDIV2. This means that two events must
occur before the part uses a new value for any of the double-
buffered settings. First, the new value is latched into the device
by writing to the appropriate register. Second, a new write must
be performed on Register R0.
For example, updating the fractional value can involve a write to
the 13 LSB bits in R1 and the 12 MSB bits in R0. R1 should be
written to first, followed by the write to R0. The frequency change
begins after the write to R0. Double buffering ensures that the
bits written to in R1 do not take effect until after the write to R0.
Table 6. C3, C2, and C1 Truth Table
Control Bits
C3 C2 C1 Register
0 0 0 R0
0 0 1 R1
0 1 0 R2
0 1 1 R3
1 0 0 R4
1 0 1 R5
1 1 0 R6
1 1 1 R7
Rev. G | Page 12 of 36

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