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IR3521 Schematic ( PDF Datasheet ) - International Rectifier

Teilenummer IR3521
Beschreibung XPHASE3 AMD SVID CONTROL IC
Hersteller International Rectifier
Logo International Rectifier Logo 




Gesamt 30 Seiten
IR3521 Datasheet, Funktion
www.DataSheet4U.com
IR3521
DATA SHEET
XPHASE3TM AMD SVID CONTROL IC
DESCRIPTION
The IR3521 Control IC combined with an xPHASE3TM Phase IC provides a full featured and flexible way to
implement a complete AMD SVID power solution. It provides outputs for both the VDD core and VDDNB
auxiliary planes required by the CPU. The IR3521 provides overall system control and interfaces with any
number of Phase ICs each driving and monitoring a single phase. The xPHASE3TM architecture results in a
power supply that is smaller, less expensive, and easier to design while providing higher efficiency than
conventional approaches.
FEATURES
2 converter outputs for the AMD processor VDD core and VDDNB auxiliary planes
Supports High Speed (HS) I2C Serial communications
PSI_L serial commands are communicated to a programmable number of phase ICs
0.5% overall system set point accuracy
High speed error amplifiers with wide bandwidth of 20MHz and fast slew rate of 10V/us
Remote sense amplifiers provide differential sensing and require less than 50uA bias current
Programmable Dynamic VID Slew Rates
Programmable VID Offset (VDD output only)
Programmable output impedance (VDD output only)
Programmable Dynamic OC for IDD_Spike
Programmable per phase switching frequency of 250kHz to 1.5MHz
Hiccup over current protection with delay during normal operation
Central over voltage detection and communication to phase ICs through IIN (ISHARE) pin
OVP disabled during dynamic VID down to prevent false triggering
Over voltage signal to system with over voltage detection during powerup and normal operation
Detection and protection of open remote sense lines
Gate Drive and IC bias linear regulator control with programmable output voltage and UVLO
Small thermally enhanced 32L MLPQ (5mm x 5mm) package
ORDERING INFORMATION
Device
IR3521MTRPBF
IR3521MPBF (Samples Only)
Package
32 Lead MLPQ (5 x 5 mm body)
32 Lead MLPQ (5 x 5 mm body)
Order Quantity
3000 per reel
100 piece strips
Page 1
V3.03






IR3521 Datasheet, Funktion
IR3521www.DataSheet4U.com
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
4.75V VCCL 7.5V, -0.3V VOSEN-x 0.3V, 0 oC TJ 100 oC, 7.75 kΩ ≤ ROSC 50 k, CSS/DELx = 0.1uF
ELECTRICAL CHARACTERISTICS
The electrical characteristics table shows the spread of values guaranteed within the recommended operating conditions (unless
otherwise specified). Typical values (TYP) represent the median values, which are related to 25°C.
PARAMETER
SVID Interface
SVC & SVD Input Thresholds
Bias Current
SVD Low Voltage
SVD Fall Time, CSVD=400 pF
SVD Fall Time, CSVD=100 pF
Pulse width input filter
TEST CONDITION
Threshold Increasing
Threshold Decreasing
Threshold Hysteresis
0V V(x) 3.5V, SVD not asserted
I(SVD)= 3mA
70-30% VDDIO, 1.425V VDDIO 1.9V,
1.7MHz operation, Note 1
3.4MHz operation
Note 1
PSI_L OUTPUT
Output Voltage
Pull-up Resistance (to VCCL)
Oscillator
PHSOUT Frequency
I(PSI_L) = 3mA
ROSC Voltage
CLKOUT High Voltage
I(CLKOUT)= -10 mA, measure V(VCCL) –
V(CLKOUT).
CLKOUT Low Voltage
I(CLKOUT)= 10 mA
PHSOUT High Voltage
I(PHSOUT)= -1 mA, measure V(VCCL) –
V(PHSOUT)
PHSOUT Low Voltage
I(PHSOUT)= 1 mA
PHSIN Threshold Voltage
Compare to V(VCCL)
VDRP1 Buffer Amplifier
Input Offset Voltage
V(VDRP1) – V(IIN1), 0.5V V(IIN) 3.3V
Source Current
0.5V V(IIN1) 3.3V
Sink Current
0.5V V(IIN1) 3.3V
Unity Gain Bandwidth
Note 1
Slew Rate
Note 1
IIN Bias Current
Remote Sense Differential Amplifiers
Unity Gain Bandwidth
Note 1
Input Offset Voltage
0.5VV(VOSENx+) - V(VOSENx-) 1.6V,
Note 2
Source Current
0.5VV(VOSENx+) - V(VOSENx-) 1.6V
Sink Current
0.5VV(VOSENx+) - V(VOSENx-) 1.6V
Slew Rate
0.5VV(VOSENx+) - V(VOSENx-) 1.6V
VOSEN+ Bias Current
TBS V < V(VOSENx+) < 1.6V
VOSEN- Bias Current
-0.3V VOSENx- 0.3V, All VID Codes
VOSEN+ Input Voltage Range
V(VCCL)=7V
Low Voltage
V(VCCL) =7V
High Voltage
V(VCCL) – V(VOUTx)
MIN
0.8025
570
150
-5
20
10
6
-10%
0.57
30
-8
2
0.2
-2
3.0
-3
0.5
2
2
TYP MAX UNIT
0.90 0.9975 V
650 750 mV
250 400 mV
0 5 uA
20 300 mV
40 160 ns
20 80 ns
20 20 ns
<100
150 300 mV
10 20 k
See
Figure 2
0.600
50
+10%
0.630
1
1
1
1
70
kHz
V
V
V
V
V
%
0 8 mV
30 mA
0.4 0.6 mA
8 MHz
4.7 V/s
-0.2 1 A
6.4 9.0 MHz
0 3 mV
1 1.7 mA
12 18 mA
4 8 V/us
30 50 uA
30 50 uA
5.5 V
250 mV
0.5 1 V
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V3.03

6 Page









IR3521 pdf, datenblatt
www.DataSheet4U.com
IR3521
Control IC CLKOUT
(Phase IC CLKIN)
Control IC PHSOUT
(Phase IC1 PHSIN)
Phase IC1
PWM Latch SET
Phase IC 1 PHSOUT
(Phase IC2 PHSIN)
Phase IC 2 PHSOUT
(Phase IC3 PHSIN)
Phase IC 3 PHSOUT
(Phase IC4 PHSIN)
Phase IC4 PHSOUT
(Control IC PHSIN)
Figure 5 Four Phase Oscillator Waveforms
PWM Operation
The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock, the PWM latch is set
and the PWM ramp amplitude begins to increase prompting the low side driver is turned off. After the non-overlap
time (GATEL < 1.0V), the high side driver is turned on. When the PWM ramp voltage exceeds the error amplifier’s
output voltage, the PWM latch is reset. This also turns off the high side driver, turns on the low side driver after the
non-overlap time and the PWM ramp discharged current is clamped which quickly discharges the internal capacitor
to the output voltage of share adjust amplifier, in phase IC, until the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode
input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required.
It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of
most systems. The inductor current will increase much more rapidly than decrease in response to load transients.
This control method is designed to provide “single cycle transient response” where the inductor current changes in
response to load transients within a single switching cycle maximizing the effectiveness of the power train and
minimizing the output capacitor requirements. An additional advantage of the architecture is that differences in
ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC.
Figure 6 depicts PWM operating waveforms under various conditions.
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