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PDF BUK9MPP-65PLL Data sheet ( Hoja de datos )
| Número de pieza | BUK9MPP-65PLL | |
| Descripción | Dual TrenchPLUS FET Logic Level FET | |
| Fabricantes | NXP Semiconductors | |
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BUK9MPP-65PLL
Dual TrenchPLUS FET Logic Level FET
Rev. 01 — 27 May 2010
www.DataSheet4U.com
Objective data sheet
1. Product profile
1.1 General description
Dual N-channel enhancement mode field-effect power transistor in SO20. Device is
manufactured using NXP High-Performance (HPA) TrenchPLUS technology, featuring
very low on-state resistance, integrated current sensing transistors and over temperature
protection diodes.
1.2 Features and benefits
Integrated current sensors
Integrated temperature sensors
1.3 Applications
Lamp switching
Motor drive systems
Power distribution
Solenoid drivers
1.4 Quick reference data
Table 1. Quick reference data
Symbol Parameter
Conditions
FET1 and FET2 static characteristics
RDSon
drain-source
on-state
resistance
VGS = 5 V; ID = 5 A; Tj = 25 °C;
see Figure 17; see Figure 16
ID/Isense
ratio of drain
current to sense
current
Tj = 25 °C; VGS = 5 V;
see Figure 18
V(BR)DSS
drain-source
breakdown
voltage
ID = 250 µA; VGS = 0 V;
Tj = 25 °C
Min Typ Max Unit
- 23 27 mΩ
3587 3986 4385 A/A
65 - - V
1 page  
NXP Semiconductors
www.DataSheet4U.com
BUK9MPP-65PLL
Dual TrenchPLUS FET Logic Level FET
103
ID
(A)
102
10
1
10−1
10−2
10−1
Limit RDSon = VDS / ID
DC
001aal756
tp = 10 μs
100 μs
1 ms
10 ms
100 ms
1 10 102
VDS (V)
Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
Rth(j-sp)
Rth(j-a)
Thermal characteristics
Parameter
thermal resistance
from junction to solder
point
thermal resistance
from junction to
ambient
Conditions
FET1
FET2
mounted on a printed-circuit board; both
channels conducting; zero heat sink
area; see Figure 5; see Figure 6
mounted on a printed-circuit board; both
channels conducting; 200 mm² copper
heat sink area;
see Figure 7; see Figure 6
mounted on a printed-circuit board; both
channels conducting; 400 mm² copper
heat sink area;
see Figure 8; see Figure 6
mounted on a printed-circuit board; one
channel conducting; zero heat sink
area; see Figure 5; see Figure 6
mounted on a printed-circuit board; one
channel conducting; 200 mm² copper
heat sink area;
see Figure 7; see Figure 6
mounted on a printed-circuit board; one
channel conducting; 400 mm² copper
heat sink area; see Figure 8
Min Typ Max Unit
- - 33 K/W
- - 33 K/W
- 73 - K/W
- 60 - K/W
- 51 - K/W
- 105 - K/W
- 90 - K/W
- 70 - K/W
BUK9MPP-65PLL
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 27 May 2010
© NXP B.V. 2010. All rights reserved.
5 of 17
5 Page 
NXP Semiconductors
003aad921
2
a
1.5
1
0.5
0
-60 0 60 120 180
Tj ( C)
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BUK9MPP-65PLL
Dual TrenchPLUS FET Logic Level FET
001aal776
100
RDSon
(mΩ) 2.5
3.0
3.5
4.0 4.5
80
5.0
60
40
VGS (V) = 10 V
20
0
0 20 40 60 80 100
ID (A)
Fig 16. Normalized drain-source on-state resistance
factor as a function of junction temperature,
FET1 and FET2
8000
ID/Is ens e
003aad913
6000
4000
2000
Fig 17. Drain-source on-state resistance as a function
of drain current; typical values, FET1 and FET2
4
VF(TS D)
3
003aad914
2
0
2 4 6 8 10
VGS (V)
1
0 50 100 150
Tj ( C)
Fig 18. Ratio of drain current to sense current as a
function of gate-source voltage; typical values,
FET1 and FET2
Fig 19. Temperature sense diode forward voltage as a
function of junction temperature; typical
values, FET1 and FET2
BUK9MPP-65PLL
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 27 May 2010
© NXP B.V. 2010. All rights reserved.
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