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S71JL064H80 Schematic ( PDF Datasheet ) - Advanced Micro Devices

Teilenummer S71JL064H80
Beschreibung Stacked Multi-chip Product (MCP) Flash Memory And Psram CMOS 3.0Volt-only
Hersteller Advanced Micro Devices
Logo Advanced Micro Devices Logo 




Gesamt 30 Seiten
S71JL064H80 Datasheet, Funktion
S71JL128HC0/128HB0/064HB0/
064HA0/064H80
Stacked Multi-Chip Product (MCP) Flash Memory
and pSRAM CMOS 3.0 Volt-only,
Simultaneous Operation Flash Memories and
Static RAM/Pseudo-static RAM
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PRELIMINARY
DISTINCTIVE CHARACTERISTICS
MCP Features
„ Operating Voltage Range of 2.7 to 3.3 V
„ High Performance
— Access time as fast as 55 ns
„ Packages
— 73-ball FBGA—8 x 11.6 mm
— 88-ball FBGA—8 x 11.6 mm
„ Operating Temperatures
— Wireless: –25°C to +85°C
— Industrial: –40°C to +85°C
GENERAL DESCRIPTION
The S71JLxxxH Series is a product line of stacked Multi-Chip
Products (MCP) and consists of
„ One or more S29JL064H Flash devices
„ SRAM or pSRAM options
— 8Mb x 8/x 16 SRAM
— 16Mb x 16-only SRAM
— pSRAM x 16 only:
8Mb pSRAM
16Mb pSRAM
32Mb pSRAM
64Mb pSRAM
The products covered by this document are listed below. For
details about their specifications, please refer to the individual
constituent data sheets for further details.
MCP
Number of S29JL064H
Total Flash Density
SRAM/pSRAM Density
S71JL064H80
1
64Mb
8Mb
S71JL064HA0
1
64Mb
16Mb
S71JL064HB0
1
64Mb
32Mb
S71JL128HB0
2
128Mb
32Mb
S71JL128HC0
2
128Mb
64Mb
Notes:
1. This MCP is only guaranteed to operate @ 2.7 - 3.3 V regardless of component operating ranges.
2. BYTE# operation is only supported on the S71JL064H80xx0x.
Publication Number S29JLxxxHxx_00 Revision A Amendment 2 Issue Date February 26, 2004






S71JL064H80 Datasheet, Funktion
Preliminary
Block Diagrams
MCP Block Diagram of S71JL064H80, Model Numbers 01/02
A21 to A0
A–1
WP#/ACC
RESET#
CE#f
CIOf
A21 to A0
VCCf VSS
RY/BY#
64 MBit
Flash Memory
DQ15/A-1 to DQ0
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VCCs VSS
DQ15/A–1 to DQ0
SA
LB#
UB#
WE#
OE#
CE1#s
CE2s
CIOs
AA018totoA1A90
8 MBit
SRAM
DQ15/A-1 to DQ0
MCP Block Diagram of S71JL064H80, Model Numbers 10/11/12
A21 to A0
WP#/ACC
RESET#
CE#f
A21 to A0
VCCf VSS
64 MBit
Flash Memory
RY/BY#
DQ15 to DQ0
LB#
UB#
WE#
OE#
CE1#s
CE2s
VCCs VSS
AA018totoA1A90
8 MBit
PSRAM
RY/BY#
DQ15 to DQ0
DQ15 to DQ0
6 S71JLxxxHxx_00A1 February 25, 2004

6 Page









S71JL064H80 pdf, datenblatt
Preliminary
www.DataSheet4U.com
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages
(FBGA). The package and/or data integrity may be compromised if the package
body is exposed to temperatures above 150°C for prolonged periods of time.
Pin Description
A18–A0
A21–A19, A-1
SA
DQ15–DQ0
CE#f
CE#s
OE#
WE#
RY/BY#
UB#
LB#
CIOf
=
=
=
=
=
=
=
=
=
=
=
=
CIOs
=
RESET#
WP#/ACC
VCCf
VCCs
VSS
NC
=
=
=
=
=
=
19 Address Inputs (Common)
4 Address Inputs (Flash)
Highest Order Address Pin (SRAM) Byte mode
16 Data Inputs/Outputs (Common)
Chip Enable (Flash)
Chip Enable (SRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Output
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
I/O Configuration (Flash)
CIOf = VIH = Word mode (x16),
CIOf = VIL = Byte mode (x8)
I/O Configuration (SRAM)
CIOs = VIH = Word mode (x16),
CIOs = VIL = Byte mode (x8)
Hardware Reset Pin, Active Low
Hardware Write Protect/Acceleration Pin (Flash)
Flash 3.0 volt-only single power supply (see Product
Selector Guide for speed options and voltage supply
tolerances)
SRAM Power Supply
Device Ground (Common)
Pin Not Connected Internally
12 S71JLxxxHxx_00A1 February 25, 2004

12 Page





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