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TDA10023HT Schematic ( PDF Datasheet ) - Philips

Teilenummer TDA10023HT
Beschreibung Single chip DVB-C/MCNS channel receiver
Hersteller Philips
Logo Philips Logo 




Gesamt 20 Seiten
TDA10023HT Datasheet, Funktion
www.DataSheet4U.com
TDA10023HT
Single chip DVB-C/MCNS channel receiver
Rev. 01 — 12 April 2005
Product data sheet
1. General description
The TDA10023HT is a single chip DVB-C/MCNS channel receiver for 4, 16, 32, 64, 128
and 256-QAM modulated signals. The device interfaces directly to the IF signal, which is
sampled by a 10-bit A/D converter.
The TDA10023HT performs the clock and the carrier recovery functions. The digital loop
filters for both clock and carrier recovery are programmable in order to optimize their
characteristics according to the current application.
After baseband conversion, equalization filters are used for echo cancellation in cable
applications. These filters are configured as T-spaced transversal equalizer or DFE
equalizer, so that the system performance can be optimized according to the network
characteristics. A proprietary equalization algorithm, independent of carrier offset, is
achieved in order to assist carrier recovery. Then a decision directed algorithm takes
place, to achieve final equalization convergence.
The TDA10023HT chip implements two FEC decoders, one for each standard. In the
DVB-C mode the TDA10023HT implements a Forney convolutional de-interleaver of depth
12 blocks and a Reed-Solomon decoder which corrects up to 8 erroneous bytes. The
de-interleaver and the Reed-Solomon decoder are automatically synchronized thanks to
the frame synchronization algorithm that uses the MPEG2 sync byte. Finally descrambling
according to DVB-C standard is achieved at the Reed-Solomon output. In the MCNS
mode the receiver error correction implements a soft decision trellis decoder to correct
random channel errors, a randomizer, a convolutional de-interleaver of depth I = 128, 64,
32, 16, 8 and J = 1, 2, 3, 4, 8, 16 for burst protection, and a Reed-Solomon decoder which
corrects up to 3 erroneous symbols. The de-interleaver and the Reed-Solomon decoder
are automatically synchronized using the frame sync trailer.
This device is controlled via an I2C-bus.






TDA10023HT Datasheet, Funktion
Philips Semiconductors
7. Pinning information
7.1 Pinning
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TDA10023HT
Single chip DVB-C/MCNS channel receiver
VDDA1 1
XIN 2
XOUT 3
VSSA1 4
SACLK 5
TEST 6
VDDD3
VSSD3
AGCTUN
7
8
9
IICDIV 10
AGCIF 11
SADDR 12
n.c. 13
VDDD2 14
VSSD2 15
CLRB 16
TDA10023HT
48 DO[0]
47 DO[1]
46 DO[2]
45 DO[3]
44 VSSD2
43 VDDD2
42 VSSD3
41 VDDD3
40 DO[4]
39 DO[5]
38 DO[6]
37 DO[7]
36 DEN
35 OCLK
34 PSYNC
33 UNCOR
001aac556
Fig 2. Pin configuration
7.2 Pin description
9397 750 14559
Product data sheet
Table 3:
Symbol
VDDA1
XIN
XOUT
VSSA1
SACLK
TEST
Pin description
Pin Type [1] Description
1 S crystal analog supply voltage 1.8 V
2 I Crystal oscillator input. Typically a fundamental crystal oscillator
is connected between the XIN and XOUT pins. The crystal
frequency must be chosen so that the system frequency
SYSCLK (= XIN × multiplying factor of the PLL) equals 1.6
times the tuner output intermediate frequency: SYSCLK = 1.6 ×
IF.
3 O crystal oscillator output; typically a fundamental crystal
oscillator is connected between the XIN and XOUT pins
4 G crystal analog ground
5 O Sampling clock. This output clock can be fed to an external
10-bit ADC as the sampling clock. SACLK can be either equal
to SYSCLK/2 in simple sampling mode or equal to SYSCLK in
double sampling mode.
6 I test input pin; in normal mode, TEST must be grounded
Rev. 01 — 12 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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TDA10023HT pdf, datenblatt
Philips Semiconductors
www.DataSheet4U.com
TDA10023HT
Single chip DVB-C/MCNS channel receiver
9.3 Crystal oscillator
TDA10023HT
XIN XOUT
23
XTAL
C1 C2
001aac559
(1) Typical crystal is on fundamental frequency (typically 16 MHz).
(2) Values of passive components are dependant on crystal manufacturer (typically C1 = C2 = 56 pF).
Fig 5. Typical crystal connection
9.4 External AGC circuitry
TDA10023HT
AGCTUN/ 9
AGCIF 11
R
to TUNER/IF
C
001aac560
(1) R and C are chosen to verify SR/1024 < fc << XIN/16 with R = 1.5 kand C = 1 nF, fc = 100 kHz.
Fig 6. External AGC connection
9397 750 14559
Product data sheet
Rev. 01 — 12 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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