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IXA531 Schematic ( PDF Datasheet ) - IXYS

Teilenummer IXA531
Beschreibung 500mA 3-Phase Bridge Driver
Hersteller IXYS
Logo IXYS Logo 




Gesamt 11 Seiten
IXA531 Datasheet, Funktion
IXA531
500mA 3-Phase Bridge Driver
Preliminary Data Sheet
www.DataSheet4U.com
Features
Fully operational to +650V
• Tolerant of negative transient voltages
• dV/dt immune (50V/ns)
• Latch-up protected over entire operating range
• Fault-current shutdown for all drive outputs
• User selectable delay or latching function for
clearing of the FAULT signal, independent
user controlled clearing of the FAULT signal
is also available
• UVLO protection for all drive outputs
• Enable signal capable of disabling all driver outputs
• 3 half-bridge driver pairs (independent)
• 3.3V logic compatible
• Cross-conduction prevention logic,
220 ns - 360ns Phase leg deadtime
• Peak output current: 600mA Pull-up/Source,
600mA Pull-down/Sink
• Wide operating supply voltage range: 8.0V to 35V
• Capacitive load drive capability: 1250pF in < 100ns
• Matched, low propagation delay times
• Low supply current
• Monolithic construction
___
• Fault monitoring is accompanied by a FLT
signal indication, with programmable reset or user
selectable latched protection
• Target package power dissipation capability is 2.0W.
• Full level of function available from -55°C to + 125°C
Available in 48-Lead 7mm x 7mm MLP Quad
package and 44-Lead PLCC package
General Description
The IXA531 is a monolithic, 3-phase, MOSFET/IGBT
gate driver consisting of three independent, high and low
side output channels. In addition to the six inputs,
which are CMOS/TTL Compatible, for the three
corresponding high side and three low side outputs,
there are dedicated lines for FAULT, ENABLE and
RESET. Overload/Short Circuit protection is
implemented by sensing a voltage across a shunt or low
value resistor which carries load current. Upon
Overload/Short Circuit detection, all outputs are
disabled. Likewise ENABLE (EN) pin, when LOW under
abnormal operating conditions, affords soft shut down of
outputs. FAULT(FLT) signal‘s status indicates that shut
down has occurred either due to Overload/Short Circuit
in driven MOSFET/IGBT or Under Voltage on VCL.
Clearing of FAULT (FLT) signal and restoration of
normal operation ensue automatically after a
programmed delay using an RC Network wired at RST
(RESET) pin. Matched propagation delays ensure
proper operation even at very high switching
frequencies. Absence of cross conduction in output
stages removes possibility of shoot through in driven
power MOSFETs or IGBTs.
Applications
• Driving MOSFETs and IGBTs in half-bridge circuits
• High voltage, high side and low side drivers
• Motor Controls
• Switch Mode Power Supplies (SMPS)
• DC to DC Converters
• Class D Switching Amplifiers
Ordering Information
Part
IXA531S10
IXA531L4
Package
48L - SSLGA
44L - PLCC
Copyright © IXYS CORPORATION 2005
Warning: The IXA531 is ESD sensitive.
1 First Release
DS99187A(12/05)






IXA531 Datasheet, Funktion
IXA531
Dynamic Electrical Characteristics
www.DataSheet4U.com
VCL = VCH = VBIAS = 15V, VHS1,2,3 = VDG = VLS, TA = 25°C and CL = 1000pF unless otherwise specified.
Symbol Definition
Min. Typ. Max. Units Test Conds.
ton
toff
tr
tf
tEN
tITRP
tbl
tFLT
tFILIN
tFLCLR
DT
MT
MDT
PM
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Turn-on fall time
ENABLE low to output shutdown
propagation delay
ITRP to output shutdown propagation delay
ITRP blanking time
ITRP to FAULT propagation delay
Input filter time (HIN, LIN, EN)
FAULT clear time RST=2meg, C=1nF
Dead time
Matching delay ON and OFF
Matching delay, max (ton , toff) - min (ton , toff)
(ton,toff are applicable to all 3 channels)
Output pulse width matching, PWMIN-PWMOUT
300 425 550 nS VIN=0V & 5V
250 400 550 nS VIN=0V & 5V
125 190
nS
----
50 75 nS
----
300 450 600 nS VIN , VEN = 0 V
or 5 V
500
750 1000
nS
VITRP=5V
100 150
nS VIN=0V or 5V
VITRP = 5V
400 600 800
nS V IN = 0V or 5V
VITRP = 5V
100 200
nS VIN = 0V & 5V
1.3 1.65 2
mS VIN = 0V or 5V
VITRP=0V
220 290 360 nS VIN = 0V & 5V
40 75 nS External Dead
25 70
nS Time
>400nsec
40 75 nS
VCL
<UVCL
15V
15V
15V
15V
VCH
X
<UVCH
15V
15V
15V
ITRP
X
0V
0V
>VITRP
0V
ENABLE
X
15V
15V
15V
0V
FAULT
0(note 1)
high imp
high imp
0 (note 2)
high imp
LGO1,2,3
0
LIN1,2,3
LIN1,2,3
0
0
HGO1,2,3
0
0
HIN1,2,3
0
0
Notes: A Cross Conduction logic prevents LGO1,2,3 and HGO1,2,3 for each channel from turning on
simultaneously.
1. UVCL is not latched, when VCL>UVCL, FAULT returns to high impedance.
2. When ITRP < VITRP, FAULT returns to high-impedance after RST pin becomes greater then 8V
(@VCL= 15V).
6

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