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AD5061 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5061
Beschreibung 16-Bit Vout nanoDAC Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 17 Seiten
AD5061 Datasheet, Funktion
Preliminary Technical Data
FEATURES
Single 16-Bit DAC, 4 Lsb inl.
1.8 Volt Digital Interface Capability
Power-On-Reset to Zero Volts/Mid Scale
Three Power-Down Functions
Low Power Serial Interface with Schmitt-
Triggered Inputs
8-Lead Sot23
Low Power Operation
Fast Settling.
Low Glitch on Powerup.
16 Bit 4LSB Vout nanoDacTM,
Buffered, 3V/5V, Sot 23www.DataSheet4U.com
AD5061
APPLICATIONS
Process Control
Data Acquisition Systems
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The AD5061, a member of the nanoDACTM family, is a single
16-bit buffered voltage out DAC, available in a 8 ld Sot23. The
AD5061 can be operated at 3V/5V.
The part utilizes a versatile three-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI™, QSPI™, MICROWIRE™ and DSP interface
standards.
The reference for the AD5061 is supplied from an external
REF pin. A reference buffer is also provided on chip. The parts
incorporate a power-on-reset circuit that ensures that the DAC
output powers up to zero volts/ mid scale and remains there
until a valid write takes place to the device. The parts also
contain a power-down feature that reduces the current
consumption of the device to 50nA at 5 V and provides
software selectable output loads while in power-down mode.
The part is put into power-down mode over the serial interface.
Total unadjusted error for the part is <1mV.
These parts also provide a very low glitch on power-up.
AD5061
Part Number
AD5062
AD5063
Description
2.7 V to 5.5 V, 16 Bit nanoDACTM D/A, 1LSBs INL.,
Unbuffered, Sot 23.
2.7 V to 5.5 V, 16 Bit nanoDACTM D/A, 1 LSBs INL.,
Unbuffered, 10 uSOIC, uncommitted bi-polar resistors.
AD5040/60
2.7 V to 5.5 V, 14/16 Bit nanoDACTM D/A, 1 LSBs
INL, Buffered, Sot23.
PRODUCT HIGHLIGHTS
1. Available in 8-lead SOT23.
2. 16 Bit Accurate, 4 LSB INL.
3. Low Glitch on Power-up.
4. High speed serial interface with clock speeds up to 30 MHz.
5. Three power down modes available to the user.
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
Rev. Prb | Page 1 of 17






AD5061 Datasheet, Funktion
AD5061
PIN CONFIGURATION AND FUNCTION
DESCRIPTION
Preliminary Technical Data
www.DataSheet4U.com
Figure 2. AD5063 8 ld SOT23
Table 2. Pin Function Descriptions
Mnemonic Function
VDD Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and VDD should be decoupled to GND.
REF Reference Voltage Input.
DacGND
VOUT
SYNC
SCLK
DIN
AGND
Ground input to the DAC.
Analog output voltage from DAC.
Level triggered control input (active low). This is the frame synchronization signal for the input data. When SYNC goes low,
it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated
following the 16th clock cycle unless SYNC is taken high before this edge in which case the rising edge of SYNC acts as an
interrupt and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be
transferred at rates up to 30 MHz.
Serial Data Input. This device has a 24 bit shift register. Data is clocked into the register on the falling edge of the serial clock
input.
Ground reference point for Analog circuitry on the part.
Rev. PrB | Page 6 of 17

6 Page









AD5061 pdf, datenblatt
AD5061
GENERAL DESCRIPTION
The AD5061 is a single 16-bit, serial input, voltage output
DACs. The AD5061 operates from either a 3V or 5V supply.
Data is written to the AD50461in a 24-bit word format.
The AD5061 incorporates a power-on reset circuit, which
ensures that the DAC output powers up to 0 V or mid-scale. The
device also has a software power-down mode pin, which
reduces the typical current consumption to 50nA at 3V.
DAC Architecture
The DAC architecture of the AD5061 consists of two matched
DAC sections. A simplifed circuit diagram is shown in Figure X
The four MSBs of the 16-bit data word are decoded to drive 15
switches, E1 to E15. Each of these switches connects one of 15
matched resistors to either AGND or VREF. The remaining 12
bits of thedata word drive switches S0 to S11 of a 12-bit voltage
modeR-2R ladder network.
Figure X. DAC Ladder Structure
Reference Buffer
The AD5061 operates with an external reference. The
reference input (REFIN) has an input range of up to Vdd.
This input voltage is then used to provide a buffered
Preliminary Technical Data
reference for the DAC core
www.DataSheet4U.com
SERIAL INTERFACE
The AD5061 (24 bit word write) has a three-wire
serial interface (SYNC, SCLK and DIN), which is
compatible with SPI, QSPI and MICROWIRE interface
standards as well as most DSPs. See Figure 1 for a timing
diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low.
Data from the DIN line is clocked into the 24-bit shift register
on the falling edge of SCLK. The serial clock frequency can be
as high as 30 MHz, making these parts compatible with high
speed DSPs. On the 24 th falling clock edge, the last data bit is
clocked in and the programmed function is executed (i.e., a
change in DAC register contents and/or a change in the mode
of operation). At this stage, the SYNC line may be kept low or
be brought high. In either case, it must be brought high for a
minimum of 33 ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence. Since
the SYNC buffer draws more current when VIN = 1.8 V than it
does when VIN = 0.8 V, SYNC should be idled low between
write sequences for even lower power operation of the part. As
is mentioned above, however, it must be brought high again
just before the next write sequence.
Input Shift Register
The input shift register is 24 bits wide (see Figure 22/23). D23-
D16 are set to zero for normal operation. D17, D16 are control
bits that control which mode of operation the part is in (normal
mode or any one of three power-down modes). There is a more
complete description of the various modes in the Power-
Down Modes section. The next sixteen bits are the data bits.
These are transferredtotheDACregisteronthe24thfallingedgeofSCLK.
Figure 22. AD5060 Input Register Contents
Rev. PrB | Page 12 of 17

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