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PDF SST34HF3244C Data sheet ( Hoja de datos )
| Número de pieza | SST34HF3244C | |
| Descripción | 32 Mbit Concurrent SuperFlash + 4/8 Mbit (P)SRAM ComboMemory | |
| Fabricantes | Silicon Storage Technology | |
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32 Mbit Concurrent SuperFlash + 4/8 Mbit (P)SRAM ComboMemory
SST34HF3242C / SST34HF3244C
SST34HF3282 / SST34HF3284
www.DataSheet4U.com
SST34HF32x4x32Mb CSF + 4/8/16 Mb SRAM (x16) MCP ComboMemory
Advance Information
FEATURES:
• Flash Organization: 2M x16 or 4M x8
• Dual-Bank Architecture for Concurrent
Read/Write Operation
– 32 Mbit Top Sector Protection
– SST34HF32x4x: 8 Mbit + 24Mbit
– SST34HF32x2x: 4 Mbit + 28 Mbit
• (P)SRAM Organization:
– 4 Mbit: 256K x16
– 8 Mbit: 512K x16
• Single 2.7-3.3V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 25 mA (typical)
– Standby Current: 20 µA (typical)
• Hardware Sector Protection (WP#)
– Protects 8 KWord in the smaller bank by holding
WP# low and unprotects by holding WP# high
• Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
data array
• Byte Selection for Flash (CIOF pin)
– Selects 8-bit or 16-bit mode
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Flash Chip-Erase Capability
• Block-Erase Capability
– Uniform 32 KWord blocks
• Erase-Suspend / Erase-Resume Capabilities
• Read Access Time
– Flash: 70 ns
– (P)SRAM: 70 ns
• Security ID Feature
– SST: 128 bits
– User: 256 bits
• Latched Address and Data
• Fast Erase and Program (typical):
– Sector-Erase Time: 18 ms
– Block-Erase Time: 18 ms
– Chip-Erase Time: 35 ms
– Program Time: 7 µs
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Packages Available
– 56-ball LFBGA (8mm x 10mm)
– 62-ball LFBGA (8mm x 10mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST34HF32x2xC/32x4x ComboMemory devices inte-
grate either a 2M x16 or 4M x8 CMOS flash memory bank
with either a 256K x16 or 512K x16 CMOS SRAM or
pseudo SRAM (PSRAM) memory bank in a multi-chip
package (MCP). These devices are fabricated using SST’s
proprietary, high-performance CMOS SuperFlash technol-
ogy incorporating the split-gate cell design and thick-oxide
tunneling injector to attain better reliability and manufactur-
ability compared with alternate approaches. The
SST34HF32x2xC/32x4x devices are ideal for applications
such as cellular phones, GPS devices, PDAs, and other
portable electronic devices in a low power and small form
factor system.
The SST34HF32x2xC/32x4x feature dual flash memory
bank architecture allowing for concurrent operations
between the two flash memory banks and the (P)SRAM.
The devices can read data from either bank while an Erase
or Program operation is in progress in the opposite bank.
The two flash memory banks are partitioned into 4 Mbit +
28 Mbit or 8 Mbit + 24 Mbit with top sector protection
options for storing boot code, program code, configuration/
parameter data and user data.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore, the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles. The SST34HF32x2xC/32x4x devices offer a
guaranteed endurance of 10,000 cycles. Data retention is
rated at greater than 100 years. With high-performance
Program operations, the flash memory banks provide a
typical Program time of 7 µsec. The entire flash memory
bank can be erased and programmed word-by-word in typ-
ically 4 seconds for the SST34HF32x2xC/32x4x, when
using interface features such as Toggle Bit, Data# Polling,
©2005 Silicon Storage Technology, Inc.
S71282-00-000
8/05
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation.
CSF and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
1 page  
32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory
SST34HF3242C / SST34HF3244C
SST34HF3282 / SST34HF3284
www.DataSheet4U.com
Advance Information
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. The toggle bit is valid after the rising edge of the fourth
WE# (or BEF#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the
rising edge of sixth WE# (or BEF#) pulse. DQ6 will be set to
“1” if a Read operation is attempted on an Erase-sus-
pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ6 will
toggle.
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bit information. The Toggle Bit (DQ2)
is valid after the rising edge of the last WE# (or BEF#)
pulse of a Write operation. See Figure 10 for Toggle Bit tim-
ing diagram and Figure 22 for a flowchart.
TABLE 1: WRITE OPERATION STATUS
Status
DQ7 DQ6
DQ2
RY/BY#
Normal Standard
Operation Program
DQ7# Toggle No Toggle
0
Standard
Erase
0 Toggle Toggle
0
Erase-
Suspend
Mode
Read From
Erase
Suspended
Sector/Block
1
1 Toggle
1
Read From
Non-Erase
Suspended
Sector/Block
Data
Data
Data
1
Program
DQ7# Toggle No Toggle
0
T1.1 1282
Note: DQ7, DQ6, and DQ2 require a valid address when reading
status information. The address must be in the bank where
the operation is in progress in order to read the operation sta-
tus. If the address is pointing to a different bank (not busy),
the device will output array data.
Data Protection
The SST34HF32x2xC/32x4x provide both hardware and
software features to protect nonvolatile data from inadvert-
ent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST34HF32x2xC/32x4x provide a hardware block
protection which protects the outermost 8 KWord/16 KByte
in Bank 1. The block is protected when WP# is held low.
When WP# is held low and a Block-Erase command is
issued to the protected block, the data in the outermost 8
KWord/16 KByte section will be protected. The rest of the
block will be erased. See Table 3 for Block-Protection loca-
tion.
A user can disable block protection by driving WP# high
thus allowing erase or program of data into the protected
sectors. WP# must be held high prior to issuing the write
command and remain stable until after the entire Write
operation has completed. If WP# is left floating, it is inter-
nally held high via a pull-up resistor, and the Boot Block is
unprotected, enabling Program and Erase operations on
that block.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode (see Figure 18). When no internal
Program/Erase operation is in progress, a minimum period
of TRHR is required after RST# is driven high before a valid
Read can take place (see Figure 17).
The Erase operation that has been interrupted needs to be
reinitiated after the device resumes normal operation mode
to ensure data integrity. See Figures 17 and 18 for timing
diagrams.
©2005 Silicon Storage Technology, Inc.
5
S71282-00-000
8/05
5 Page 
32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory
SST34HF3242C / SST34HF3244C
SST34HF3282 / SST34HF3284
PIN DESCRIPTION
www.DataSheet4U.com
Advance Information
TOP VIEW (balls facing down)
8
A15 NC NC A16 CIOF VSS
7
A11 A12 A13 A14 NC Note* DQ7 DQ14
6
A8 A19 A9 A10 DQ6 DQ13 DQ12 DQ5
5
WE# BES2 A20
4
DQ4 VDDS NC
WP# RST# RY/BY#
3
DQ3 VDDF DQ11
LBS# UBS# A18 A17 DQ1 DQ9 DQ10 DQ2
2
A7 A6 A5 A4 VSS OE# DQ0 DQ8
1
A3 A2 A1 A0 BEF# BES1#
ABCDEFGH
Note: F7 = DQ15/A-1
FIGURE 1: PIN ASSIGNMENTS FOR 56-BALL LFBGA (8MM X 10MM)
TOP VIEW (balls facing down)
8
NC A20 A11 A15 A14 A13 A12 VSSF NC NC
7
A16 A8 A10 A9 DQ15 WES# DQ14 DQ7
6
WEF# RY/BY#
5
DQ13 DQ6 DQ4 DQ5
VSSS RST#
4
DQ12 BES2 VDDS VDDF
WP# NC A19 DQ11
DQ10 DQ2 DQ3
3
LBS# UBS# OES#
DQ9 DQ8 DQ0 DQ1
2
A18 A17 A7 A6 A3 A2 A1 BES1#
1
NC NC A5 A4 A0 BEF# VSSF OEF# NC NC
ABCDEFGHJK
Note: LSE for SST34HF3244C/3284
FIGURE 2: PIN ASSIGNMENTS FOR 62-BALL LFBGA (8MM X 10MM)
©2005 Silicon Storage Technology, Inc.
11
S71282-00-000
8/05
11 Page | ||
| Páginas | Total 40 Páginas | |
| PDF Descargar | [ Datasheet SST34HF3244C.PDF ] | |
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