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ADM1068 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADM1068
Beschreibung Super Sequencer and Monitor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 26 Seiten
ADM1068 Datasheet, Funktion
Data Sheet
FEATURES
Complete supervisory and sequencing solution for up to
8 supplies
8 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
4 selectable input attenuators allow supervision of supplies to
14.4 V on VH
6 V on VP1 to VP3 (VPx)
4 dual-function inputs, VX1 to VX4 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
8 programmable driver outputs, PDO1 to PDO8 (PDOx)
Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 32-lead 7 mm × 7 mm LQFP
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
Super Sequencer and Monitor
ADM1068
FUNCTIONAL BLOCK DIAGRAM
REFOUT REFGND SDA SCL A1 A0
ADM1068
VREF
SMBus
INTERFACE
EEPROM
VX1
VX2
VX3
VX4
VP1
VP2
VP3
VH
AGND
VDDCA P
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
SEQUENCING
ENGINE
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF N-FET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
VDD
ARBITRATOR
VCCP GND
Figure 1.
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDOGND
GENERAL DESCRIPTION
The ADM1068 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple supply systems.
The device also provides up to eight programmable inputs for
monitoring undervoltage faults, overvoltage faults, or out-of-
window faults on up to eight supplies. In addition, eight
programmable outputs can be used as logic enables. Six of these
programmable outputs can also provide up to a 12 V output for
driving the gate of an N-FET that can be placed in the path of
a supply.
The logical core of the device is a sequencing engine. This state-
machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.
The ADM1068 is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can
be programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
For more information about the ADM1068 register map, refer
to the AN-721 Application Note.
Rev. D
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2005–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADM1068 Datasheet, Funktion
Data Sheet
ADM1068
Parameter
Standard (Digital Output) Mode
(PDO1 to PDO8)
VOH
VOL
IOL2
ISINK2
RPULL-UP
ISOURCE (VPx)2
Three-State Output Leakage Current
Oscillator Frequency
DIGITAL INPUTS (VXx, A0, A1)
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Current, IIH
Input Low Current, IIL
Input Capacitance
Programmable Pull-Down Current,
IPULL-DOWN
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH
Input Low Voltage, VIL
Output Low Voltage, VOL2
SERIAL BUS TIMING3
Clock Frequency, fSCLK
Bus Free Time, tBUF
Start Setup Time, tSU;STA
Stop Setup Time, tSU;STO
Start Hold Time, tHD;STA
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
Input Low Current, IIL
SEQUENCING ENGINE TIMING
State Change Time
Min Typ Max Unit Test Conditions/Comments
2.4
VPU − 0.3
0
16 20
90 100
V VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA
4.5 V
VPU to VPx = 6.0 V, IOH = 0 mA
V VPU ≤ 2.7 V, IOH = 0.5 mA
0.50 V
IOL = 20 mA
20 mA Maximum sink current per PDO pin
60 mA Maximum total sink for all PDO pins
29 kΩ Internal pull-up
2 mA Current load on any VPx pull-ups, that is, total source
current available through any number of PDO pull-up
switches configured onto any one VPx pin
10 μA VPDO = 14.4 V
110 kHz All on-chip time delays derived from this clock
2.0 V Maximum VIN = 5.5 V
0.8 V
Maximum VIN = 5.5 V
−1 μA VIN = 5.5 V
1 μA VIN = 0 V
5 pF
20 μA VDDCAP = 4.75 V, TA = 25°C, if known logic state is required
2.0 V
0.8 V
0.4 V
IOUT = −3.0 mA
400 kHz
1.3 μs
0.6 μs
0.6 μs
0.6 μs
1.3 μs
0.6 μs
300 ns
300 ns
100 ns
5 ns
1 μA VIN = 0 V
10 μs
1 At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Timing specifications are guaranteed by design and supported by characterization data.
Rev. D | Page 5 of 25

6 Page









ADM1068 pdf, datenblatt
Data Sheet
ADM1068
INPUTS
SUPPLY SUPERVISION
The ADM1068 has eight programmable inputs. Four of these are
dedicated supply fault detectors (SFDs). These dedicated inputs
are called VH and VPx (VP1 to VP3) by default. The other four
inputs are labeled VXx (VX1 to VX4) and have dual functionality.
They can be used either as SFDs, with functionality similar to the
VH and VPx, or as CMOS-/TTL-compatible logic inputs to the
device. Therefore, the ADM1068 can have up to eight analog
inputs, a minimum of four analog inputs and four digital inputs,
or a combination thereof. If an input is used as an analog input,
it cannot be used as a digital input. Therefore, a configuration
requiring eight analog inputs has no available digital inputs.
Table 6 shows the details of each input.
PROGRAMMING THE SUPPLY FAULT DETECTORS
The ADM1068 can have up to eight SFDs on its eight input
channels. These highly programmable reset generators enable the
supervision of up to eight supply voltages. The supplies can be as
low as 0.573 V and as high as 14.4 V. The inputs can be configured
to detect an undervoltage fault (the input voltage drops below a
preprogrammed value), an overvoltage fault (the input voltage
rises above a preprogrammed value), or an out-of-window fault
(the input voltage is outside a preprogrammed range). The thresh-
olds can be programmed to an 8-bit resolution in registers provided
in the ADM1068. This translates to a voltage resolution that is
dependent on the range selected.
The resolution is given by
Step Size = Threshold Range/255
Therefore, if the high range is selected on VH, the step size can
be calculated as follows:
The threshold value required is given by
VT = (VR × N)/255 + VB
where:
VT is the desired threshold voltage (undervoltage or overvoltage).
VR is the voltage range.
N is the decimal value of the 8-bit code.
VB is the bottom of the range.
Reversing the equation, the code for a desired threshold is given by
N = 255 × (VT VB)/VR
For example, if the user wants to set a 5 V overvoltage threshold
on VP1, the code to be programmed in the PS1OVTH register
(as discussed in the AN-721 Application Note) is given by
N = 255 × (5 − 2.5)/3.5
Therefore, N = 182 (1011 0110 or 0xB6).
INPUT COMPARATOR HYSTERESIS
The UV and OV comparators shown in Figure 15 are always
monitoring VPx. To avoid chatter (multiple transitions when the
input is very close to the set threshold level), these comparators
have digitally programmable hysteresis. The hysteresis can be
programmed up to the values shown in Table 6.
ULTRA
LOW
VPx
RANGE
SELECT
OV
+ COMPARATOR
VREF
GLITCH
FILTER
FAULT
OUTPUT
LOW
MID
+
UV FAULT TYPE
COMPARATOR SELECT
(14.4 V − 6.0 V)/255 = 32.9 mV
Table 5 lists the upper and lower limits of each available range,
the bottom of each range (VB), and the range itself (VR).
Table 5. Voltage Range Limits
Voltage Range (V)
0.573 to 1.375
1.25 to 3.00
2.5 to 6.0
6.0 to 14.4
VB (V)
0.573
1.25
2.5
6.0
VR (V)
0.802
1.75
3.5
8.4
Figure 15. Supply Fault Detector Block
The hysteresis is added after a supply voltage goes out of
tolerance. Therefore, the user can program the amount above
the undervoltage threshold to which the input must rise before
an undervoltage fault is deasserted. Similarly, the user can program
the amount below the overvoltage threshold to which an input
must fall before an overvoltage fault is deasserted.
Table 6. Input Functions, Thresholds, and Ranges
Input Function
Voltage Range (V)
VH High Voltage Analog Input 2.5 to 6.0
6.0 to 14.4
VPx Positive Analog Input
0.573 to 1.375
1.25 to 3.00
2.5 to 6.0
VXx High-Z Analog Input
0.573 to 1.375
Digital Input
0 to 5.0
Maximum Hysteresis
425 mV
1.02 V
97.5 mV
212 mV
425 mV
97.5 mV
Not Applicable
Voltage Resolution (mV)
13.7
32.9
3.14
6.8
13.7
3.14
Not Applicable
Glitch Filter (μs)
0 to 100
0 to 100
0 to 100
0 to 100
0 to 100
0 to 100
0 to 100
Rev. D | Page 11 of 25

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