LP2995LQ Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer	LP2995LQ
Beschreibung	DDR Termination Regulator
Hersteller	National Semiconductor
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Gesamt 13 Seiten July 2003 LP2995 DDR Termination Regulator General Description The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR- SDRAM. The device contains a high-speed operational am- plifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2995 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DDR DIMMS. Patents Pending Features n Low output voltage offset n Works with +5v, +3.3v and 2.5v rails n Source and sink current n Low external component count n No external resistors required n Linear topology n Available in SO-8, PSOP-8 or LLP-16 packages n Low cost and easy to use Applications n DDR Termination Voltage n SSTL-2 n SSTL-3 Typical Application Circuit 20039302 © 2003 National Semiconductor Corporation DS200393 www.national.com Block Diagram Description The LP2995 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2 and SSTL-3. The LP2995 is capable of sinking and sourcing current at the output VTT, regulating the voltage to equal VDDQ / 2. A buffered reference voltage that also tracks VDDQ / 2 is generated on the VREF pin for providing a global reference to the DDR-SDRAM and Northbridge Chipset. VTT is designed to track the VREF voltage with a tight tolerance over the entire current range while preventing shoot through on the output stage. Series Stub Termination Logic (SSTL) was created to im- prove signal integrity of the data transmission across the memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR RAM. The most common form of termination is Class II single parallel termination. This involves using one Rs series resistor from the chipset to the memory and one Rt termination resistor. This implementa- tion can be seen below in Figure 1. 20039301 Typical values for RS and RT are 25 Ohms although these can be changed to scale the current requirements from the LP2995. For determination of the current requirements of DDR-SDRAM termination please refer to the accompanying application notes. FIGURE 1. 20039308 www.national.com 6 6 Page Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead LLP Package (LD) NS Package Number LQA16A www.national.com 8-Lead PSOP Package (PSOP-8) NS Package Number MRA08A 12 12 Page
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Besondere Datenblatt

Teilenummer	Beschreibung	Hersteller
LP2995LQ	DDR Termination Regulator	National Semiconductor
LP2995LQ	DDR Termination Regulator	National Semiconductor
LP2995LQX	DDR Termination Regulator	National Semiconductor
LP2995LQX	DDR Termination Regulator	National Semiconductor

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