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H55S1G22MFP-60 Schematic ( PDF Datasheet ) - Hynix Semiconductor

Teilenummer H55S1G22MFP-60
Beschreibung 1Gb (32Mx32bit) Mobile SDRAM
Hersteller Hynix Semiconductor
Logo Hynix Semiconductor Logo 




Gesamt 30 Seiten
H55S1G22MFP-60 Datasheet, Funktion
www.DataSheet4U.com
1GBit MOBILE SDR SDRAMs based on 8M x 4Bank x32 I/O
Specification of
1Gb (32Mx32bit) Mobile SDRAM
Memory Cell Array
- Organized as 4banks of 8,388,608 x32
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.2 / Jun. 2008
1






H55S1G22MFP-60 Datasheet, Funktion
11www.DataSheet4U.com
1Gbit (32Mx32bit) Mobile SDR Memory
H55S1G(2/3)2MFP Series
BALL DESCRIPTION
12 34
678 9
A DQ
26
DQ
24
VSS
B DQ
28
VDDQ VSSQ
C VSSQ
DQ
27
DQ
25
D VSSQ
DQ
29
DQ
30
E VDDQ
DQ
31
NC
F VSS
DQM
3
A3
G A4 A5 A6
VDD
DQ
23
VDDQ VSSQ
DQ
21
DQ
19
DQ
22
DQ
20
VDDQ
DQ
17
DQ
18
VDDQ
NC
DQ
16
VSSQ
A2
DQM
2
VDD
A10 A0
A1
TOPH A7 A8 A12
A13
BA
1
A11
VIEWJ CLK CKE
A9
BA
0
/CS /RAS
K DQM
1
NC
NC
L VDDQ
DQ
8
VSS
/CAS
VDD
/WE
DQM
0
DQ
7
VSSQ
M VSSQ
DQ
10
DQ
9
DQ
6
DQ
5
VDDQ
N VSSQ
DQ
12
DQ
14
P DQ
11
VDDQ VSSQ
DQ
1
VDDQ
DQ
3
VDDQ
VSSQ
DQ
4
R DQ
13
DQ
15
VSS
VDD
DQ
0
DQ2
Rev 1.2 / Jun. 2008
6

6 Page









H55S1G22MFP-60 pdf, datenblatt
11www.DataSheet4U.com
1Gbit (32Mx32bit) Mobile SDR Memory
H55S1G(2/3)2MFP Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
System Clock
Cycle Time
CAS Latency=3
CAS Latency=2
Clock High Pulse Width
Clock Low Pulse Width
Access Time From Clock CAS Latency=3
CAS Latency=2
Data-out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z Time
CLK to Data Output in
High-Z Time
CAS Latency=3
CAS Latency=2
Symbol
166MHz
Min Max
133MHz
Min Max
105MHz
Unit Note
Min Max
tCK3 6.0 1000 7.5 1000 9.5 1000 ns
tCK2 12 1000 12 1000 15 1000 ns
tCHW
tCLW
2.0 - 2.5 - 3.0 - ns 1
2.0 - 2.5 - 3.0 - ns 1
tAC3 - 5.4 - 6.0 - 7.0 ns 2, 3
tAC2 - 6.0 - 8.0 - 10 ns 2, 3
tOH 2.6 - 2.6 - 2.6 - ns 3
tDS 2.0 - 2.0 - 3.0 - ns 1
tDH 1.0 - 1.0 - 1.5 - ns 1
tAS 2.0 - 2.0 - 3.0 - ns 1
tAH 1.0 - 1.0 - 1.5 - ns 1
tCKS 2.0 - 2.0 - 3.0 - ns 1
tCKH
1.0 - 1.0 - 1.5 - ns 1
tCS 2.0 - 2.0 - 3.0 - ns 1
tCH 1.0 - 1.0 - 1.5 - ns 1
tOLZ 1.0 - 1.0 - 1.0 - ns
tOHZ3
tOHZ2
5.4 6.0 7.0 ns
6.0 8.0 10 ns
Notes :
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns
should be added to the parameter.
3. Output Load : 30pF+No termination
AC high level input voltage / low level input voltage : 1.6 / 0.2V
Input timing measurement reference level : 0.9V
Output
Z = 50
Transition time (input rise and fall time) : 0.5ns
Output timing measurement reference level : 0.9V
Output Load
Output load : CL = 30pF
CLK
30pF
1.6V
0.9V
0.2V
Input
1.6V
0.9V
0.2V
Output
tCK
tCH
tCL
tSETUP tHOLD
tAC
tOH
Rev 1.2 / Jun. 2008
12

12 Page





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