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PDF STE2004S Data sheet ( Hoja de datos )
| Número de pieza | STE2004S | |
| Descripción | 102 X 65 single-chip LCD controller/driver | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STE2004S
102 x 65 single-chip LCD controller/driver
Features
■ 102 x 65 bits display data RAM
■ Programmable MUX rate
■ Programmable frame rate
■ X,Y programmable carriage return
■ Dual partial display mode
■ Row by row scrolling
■ N-line inversion
■ Automatic data RAM blanking procedure
■ Selectable input interface:
– I2C Bus Fast and Hs-mode (read and write)
– 8000 and 8080 Parallel Interfaces (read
and write)
– 3-lines and 4-lines SPI Interface (read and
write)
– 3-lines 9 bit Serial Interface (read and
write)
■ Fully integrated configurable LCD bias voltage
generator with:
– Selectable multiplication factor (up to 5X)
– Effective sensing for high precision output
– Eight selectable temperature compensation
coefficients
■ CMOS compatible inputs
■ Fully integrated oscillator requires no external
components
■ Designed for chip-on-glass (COG)
applications.
■ Low power consumption, suitable for battery
operated systems
■ Logic supply voltage range from 1.7 to 3.6V
■ High voltage generator supply voltage range
from 1.75 to 4.5V
■ Display supply voltage range from 4.5 to 14.5V
■ Backward compatibility with STE2001/2/4
Description
The STE2004S is a low power CMOS LCD
controller driver. Designed to drive a 65 rows by
102 columns graphic display, it provides all
necessary functions in a single chip, including
on-chip LCD supply and bias voltages generators,
resulting in a minimum of externals components
and in a very low power consumption.
STE2004S features six standard interfaces
(3-lines Serial, 3-lines SPI, 4-lines SPI, 68000
Parallel, 8080 parallel and I2C) for interfacing with
the host micro-controller.
OSC_IN
OSC_OUT
FR_IN
FR_OUT
VSENSE SLAVE
VLCD
VLCDSENSE
RES
VSSAUX
VDD1,2
VSS
CO to C101
R0 to R64
OSC
MASTER
SLAVE SYNC
BIAS VOLTAGE
GENERATOR
TIMING
GENERATOR
CLOCK
COLUMN
DRIVERS
DATA
LATCHES
ROW
DRIVERS
SHIFT
REGISTER
HIGH VOLTAGE
GENERATOR
RESET
DATA
REGISTER
65 x 102
RAM
SCROLL
LOGIC
TEST
INSTRUCTION
REGISTER
DISPLAY
CONTROL
LOGIC
I2C BUS 9 Bit SERIAL 3 & 4 Line SPI Parallel 8080 Parallel 68K
TEST_MODE
TEST_VREF
ICON_MODE
EXT
SEL 3
SEL 2
SEL 1
SA1 SAO SDOUT SCLK/SCL SDIN/SDA_IN SDA_OUT DB0 E/WR R/W- RD D/C
to
DB7
CS
LR0047
January 2007
Rev 3
1/7979
www.st.com
79
1 page  
STE2004S
2 Pin description
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Table 1. Pin description
N° Pad Type
Function
R0 to R64
1-6
109-141
O LCD row driver output
C0 to C101
6-107
O LCD column driver output
VSS
VDD1
VDD2
VLCD
VLCDSENSE
192-203
156-163
164-171
205-209
204
GND Ground pads.
Supply IC positive power supply
Supply Internal generator supply voltages.
Supply Voltage multiplier output
Supply
Voltage multiplier regulation input. VLCDOUT sensing for output voltage fine
tuning
VSENSE_SLAVE 145 Supply Voltage reference for slave charge pump
VSSAUX
190-177-147 O Ground reference for pins configuration
VDD1AUX
142 O VDD1 reference for pins configuration
Interface mode selection - cannot be left floating
SEL1,2,3
SEL3
SEL2
SEL1
Interface
GND/VSSAUX GND/VSSAUX GND/VSSAUX
I2C
152
GND/VSSAUX GND/VSSAUX
VDD1
SPI 4-Lines 8 bit
153 I
154
GND/VSSAUX
VDD1
GND/VSSAUX SPI 3-Lines 8 bit
GND/VSSAUX
VDD1
VDD1
Serial 3-Lines 9 bit
VDD1
GND/VSSAUX GND/VSSAUX Parallel 8080-series
VDD1
GND/VSSAUX
VDD1
Parallel 68000-series
EXT_SET
Extended instruction set selection - cannot be left floating
151 I
Ext pad config
GND or VSSAUX
VDD1
Instruction set selected
BASIC
EXTENDED
ICON_MODE
155
Extended instruction set selection - cannot be left floating
Icon mode pad config
I
GND or VSSAUX
Icon mode status
DISBLED
VDD1
ENABLED
SDOUT
SDIN - SDAIN
180
179
O Serial and SPI data output - if unused must be left floating
I SDIN - Serial and SPI interface data input - cannot be left floating
I SDAIN - I2C bus data in - cannot be left floating
5/79
5 Page 
STE2004S
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Figure 6. Bias level generator
R VLCD
n+3
n + 4 ·VLCD
R
n+2
n + 4 ·VLCD
nR
2
n + 4 ·VLCD
R
1
n + 4 ·VLCD
R
VSS D00IN1150
providing an 1/(n+4) ratio, with n calculated from:
n= m – 3
For m = 65, n = 5, a 1/9 ratio is set.
For m = 49, n =4, a 1/8 ratio is set.
The STE2004S provides three bits (BS0, BS1, BS2) for programming the bias ratio as shown
below:
Table 2. Bias ratio programmable bits
BS2 BS1
BS0
000
001
010
011
100
101
110
111
The following table shows the bias level for m = 65 and m = 49:
n
7
6
5
4
3
2
1
0
11/79
11 Page | ||
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| PDF Descargar | [ Datasheet STE2004S.PDF ] | |
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