Datenblatt-pdf.com


STE2002 Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer STE2002
Beschreibung 81 X 128 single-chip LCD controller/driver
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 30 Seiten
STE2002 Datasheet, Funktion
www.DataSheet4U.com
STE2002
81 x 128 single-chip LCD controller/driver
Features
104 x 128 bits Display Data RAM
Programmable MUX rate
Programmable frame rate
X,Y Programmable carriage return
Dual partial display mode
Row by Row Scrolling
Automatic data RAM Blanking procedure
Selectable Input interface:
– I2C Bus Fast and Hs-mode (read and write)
– Parallel Interface (read and write)
– Serial Interface (read and write)
Fully Integrated oscillator requires no external
components
CMOS compatible inputs
Fully integrated configurable LCD bias voltage
generator with:
– Selectable multiplication factor (up to 6X)
– Effective sensing for High Precision Output
– Eight selectable temperature compensation
coefficients
Designed for chip-on-glass (COG) applications
Low power consumption, suitable for battery
operated systems
Logic supply voltage range from 1.7 to 3.6V
High voltage generator supply voltage range
from 1.75 to 4.2V
Display supply voltage range from 4.5 Vto
14.5V
Backward compatibility with STE2001
Description
The STE2002 is a low power CMOS LCD
controller driver. Designed to drive a 81 rows by
128 columns graphic display, provides all
necessary functions in a single chip, including on-
chip LCD supply and bias voltages generators,
resulting in a minimum of externals components
and in a very low power consumption. The
STE2002 features three standard interfaces
(Serial, Parallel & I2C) for ease of interfacing with
the host microcontroller.
Block diagram
CO to C127
R0 to R80 ICON
OSC_IN
OSC_OUT
VLCDIN
VLCDSENSE
VLCDOUT
RES
VSSAUX
VDD1,2
VSS
SEL1,2
SA1
OSC
TIMING
GENERATOR
COLUMN
DRIVERS
ROW
DRIVERS
BIAS VOLTAGE
GENERATOR
CLOCK
DATA
LATCHES
SHIFT
REGISTER
HIGH VOLTAGE
GENERATOR
RESET
DATA
REGISTER
104 x 128
RAM
SCROLL
LOGIC
TEST
INSTRUCTION
REGISTER
DISPLAY
CONTROL
LOGIC
TEST_1_14
ICON_MODE
EXT
BSY_FLG
I2CBUS
PARALLEL
SERIAL
SOUT
SAO SCL SDA_IN SDA_OUT DB0 to DB7 E R/W PD/C SCE SDIN SCLK SD/C
December 2006
Rev 3
1/61
www.st.com
61






STE2002 Datasheet, Funktion
Pin description
Figure 1. Chip mechanical drawing
COL 0
MARK_1
ROW 35
ROW 39.
STE2002
VLCDOUT
VLCDSENSE
VLCDIN
MARK_3
VLCDOUT
VLCDSENSE
VLCDIN
OSCOUT
TEST_14
TEST_13
TEST_12
TEST_11
VSS
COL 63
COL 64
COL 127
MARK_2
(0,0)
Y
X
MARK_4
SCL
SDAIN
SDAOUT
VSSAUX
RES
E
PD/C
D0
D1
D2
D3
D4
D5
D6
D7
R/W
VSSAUX
SCLK
SCE
SD/C
SDIN
SDOUT
BSY_FLG
VDD2
VDD2
VDD1
VDD1
OSCIN
ICON_MODE
SEL1
SEL2
EXT_SET
SA0
SA1
VSSAUX
TEST_10
TEST_9
TEST_8
TEST_7
TEST_6
TEST_5
TEST_4
TEST_3
TEST_2
TEST_1
ROW 80/ICON
ROW 79
ROW 76
www.DataSShTeEe2t40U0.c2om
6/61

6 Page









STE2002 pdf, datenblatt
Display data RAM
3 Display data RAM
www.DataSShTeEe2t40U0.c2om
The STE2002, provides an 104X128 bits Static RAM to store Display data. This is organized
into 13 (Bank0 to Bank12) banks with 128 Bytes. One of these banks (128 bits wide) can be
used for Icons. RAM access is accomplished in either one of the Bus Interfaces provided
(see below). Allowed addresses are X0 to X127 (Horizontal) and Y0 to Y12 (Vertical).
When writing to RAM, four addressing mode are provided:
• Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on the
left of the memory map. The X pointer is increased after each byte written. After the last
column address (X=X-Carriage), Y address pointer is set to jump to the following bank and
X restarts from X=0. (Fig. 6)
• Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the left
of the memory map. The Y pointer is increased after each byte written. After the last Y bank
address (Y=Y-Carriage), X address pointer is set to jump to next column and Y restarts from
Y=0 (Fig. 7).
• Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on the
right of the memory map. The X pointer is increased after each byte written. After the last
column address (X=X-Carriage), Y address pointer is set to jump to the next bank and X
restarts from X=0 (fig. 8).
• Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the
right of the memory map. The Y pointer is increased after each byte written. After the last Y
bank address (Y=Y-Carriage), the X pointer is set to jump to next column and Y restarts
from Y=0 (fig. 9).
After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always
jump to the cell with address (X;Y) = (0;0) (Fi. 10, 11, 12 & 13).
Data bytes in the memory could have the MSB either on top (D0 = 0, Fig.14) or on the
bottom (D0=1, Fig. 15).
The STE2002 provides also means to alter the normal output addressing. A mirroring of the
Display along the X axis is enabled setting to a logic one MY bit.This function doesn't affect
the content of the memory RAM. It is only related to the visualization process.
When ICON MODE=1 the Icon Row is not mirrored with MY and is not scrolled. When ICON
Mode=0 the Icon Row is like the other graphic lines and is mirrored and scrolled.
Four are the multiplex ratio available when the partial display mode is disabled (MUX 33,
MUX 49, MUX 65 and MUX 81).
Only a subset of writable rows are output on Row drivers.
When Y-Carriage<MUX/8, if Mux 65 is selected only the first 65 memory rows are
visualized, if Mux 49 is selected only the first 49 memory rows are visualized, if Mux 33 is
selected only the first 33 memory rows are visualized. All unused Row and Column drivers
must be left floating.
When Y-Carriage<MUX/8, the icon Bank is located to BANK 10 in MUX 81 Mode, to
BANK8 in MUX 65 Mode, to BANK 6 in MUX 49 Mode and to BANK 4 in MUX 33 Mode.
When Y-Carriage>MUX/8 lines only 33, 49, 65 or 81 lines are visualized but it is possible to
select which lines of DDRAM are connected on the output drivers. The DDRAM rows to
visualized can be selected in the 0-Y-Carriage*8 range using the scrolling function.
12/61

12 Page





SeitenGesamt 30 Seiten
PDF Download[ STE2002 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
STE200165 X 128 SINGLE CHIP LCD CONTROLLER / DRIVERSTMicroelectronics
STMicroelectronics
STE200281 X 128 single-chip LCD controller/driverSTMicroelectronics
STMicroelectronics
STE2004102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVERSTMicroelectronics
STMicroelectronics
STE2004S102 X 65 single-chip LCD controller/driverSTMicroelectronics
STMicroelectronics
STE200796 X 68 single-chip LCD controller/driverSTMicroelectronics
STMicroelectronics

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche