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PDF HT36A2 Data sheet ( Hoja de datos )

Número de pieza HT36A2
Descripción 8-Bit Music Synthesizer MCU
Fabricantes Holtek Semiconductor 
Logotipo Holtek Semiconductor Logotipo



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No Preview Available ! HT36A2 Hoja de datos, Descripción, Manual

HT36A2
8-Bit Music SynthesizerwwMw.DCatUaSheet4U.com
Features
· Operating voltage: 2.4V~5.0V
· Operating frequency: 3.58MHz~12MHz (typ. 8MHz)
· 20 bidirectional I/O lines
· Two 8-bit programmable timer with 8 stage prescaler
· Watchdog Timer
· Built-in 8-bit MCU with 208´8 bits RAM
· Built-in 64K´16-bit ROM for program/data shared
· Mono output
· High D/A converter resolution: 16 bits
· Polyphonic up to 8 notes
· Independent volume mix can be assigned to each
sound component
General Description
The HT36A2 is an 8-bit high performance RISC-like
microcontroller specifically designed for music applica-
tions. It provides an 8-bit MCU and a 8 channel
wavetable synthesizer. The program ROM is composed
of both program control codes and wavetable voice
codes, and can be easily programmed.
Block Diagram
· Sampling rate of 25kHz as 6.4MHz for system
frequency
· Eight-level subroutine nesting
· HALT function and wake-up feature to reduce power
consumption
· Bit manipulation instructions
· 16-bit table read instructions
· 63 powerful instructions
· All instructions in 1 or 2 machine cycles
· 28-pin SOP, 48-pin SSOP package
The HT36A2 has a built-in 8-bit microprocessor which
programs the synthesizer to generate the melody by
setting the special register from 20H~2AH. A HALT fea-
ture is provided to reduce power consumption.
P A 0~P A 7
P B 0~P B 7
P C 0~P C 3
O SC1
O SC2
RES
6 4 K ´ 1 6 - b it
ROM
8 - B it 2 0 8 ´ 8
M CU RAM
VDD
VSS
VDDA
VSSA
M u ltip lie r /P h a s e
G e n e ra l
1 6 - B it
DAC
AUD
Rev. 1.00
1 June 19, 2003

1 page




HT36A2 pdf
V vs F Characteristics Curve
H T 3 6 A 2 V v s . F C h a r t (F o r 3 .0 V )
10
9
8
1 5 5 k W /8 M H z
7
6
2 0 0 k W /6 M H z
5
4
2 .4 2 .6 2 .8 3 3 .2 3 .4 3 .6 3 .8 4 4 .2 4 .4 4 .6 4 .8 5
V D D (V )
HT36A2
www.DataSheet4U.com
H T 3 6 A 2 V v s . F C h a r t (F o r 4 .5 V )
10
9
1 4 5 k W /8 M H z
8
7
6
1 9 0 k W /6 M H z
5
4
2 .4 2 .6 2 .8 3 3 .2 3 .4 3 .6 3 .8 4 4 .2 4 .4 4 .6 4 .8 5
V D D (V )
Rev. 1.00
5 June 19, 2003

5 Page





HT36A2 arduino
HT36A2
O SC1
V DD O S C 1
O SC2
C r y s ta l O s c illa to r
fS Y S /8
System oscillator
O SC2
R C O s c illa to r
with pull-high resistor, which can be used to synchronize
external logic. The RC oscillator provides the most cost
effective solution. However, the frequency of the oscilla-
tion may vary with VDD, temperature, and the chip itself
due to process variations. It is therefore, not suitable for
timing sensitive operations where accurate oscillator
frequency is desired.
On the other hand, if the crystal oscillator is selected, a
crystal across OSC1 and OSC2 is needed to provide the
feedback and phase shift required for the oscillator, and
no other external components are required. A resonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two ex-
ternal capacitors in OSC1 and OSC2 are required.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately 78ms. The WDT oscillator can
be disabled by mask option to conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock of the MCU divided by 4), determined by mask
options. This timer is designed to prevent a software
malfunction or sequence jumping to an unknown loca-
tion with unpredictable results. The Watchdog Timer can
be disabled by mask option. If the Watchdog Timer is
disabled, all the executions related to the WDT result in
no operation.
Once the internal WDT oscillator (RC oscillator with a
period of 78ms normally) is selected, it is first divided by
256 (8-stages) to get the nominal time-out period of ap-
proximately 20ms. This time-out period may vary with
temperature, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bwit w2,w1,.0DaoftathSeheet4U.com
WDTS) can give different time-out periods. If WS2,
WS1, WS0 all equal to 1, the division ratio is up to 1:128,
and the maximum time-out period is 2.6 seconds.
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. The
high nibble and bit 3 of the WDTS are reserved for user
defined flags, and the programmer may use these flags
to indicate some specified status.
WS2 WS1 WS0
Division Ratio
000
001
1:1
1:2
010
011
1:4
1:8
100
101
1:16
1:32
110
111
1:64
1:128
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit TO. Whereas in the
HALT mode, the overflow will initialize a ²warm reset²
only the PC and SP are reset to zero. To clear the WDT
contents (including the WDT prescaler ), 3 methods are
implemented; external reset (a low level to RES), soft-
ware instructions, or a HALT instruction. The software
instructions include CLR WDT and the other set - CLR
WDT1 and CLR WDT2. Of these two types of instruc-
tions, only one can be active depending on the mask op-
tion - ²CLR WDT times selection option². If the ²CLR
WDT² is selected (i.e. CLRWDT times equal one), any
execution of the CLR WDT instruction will clear the
WDT. In case ²CLR WDT1² and ²CLR WDT2² are cho-
sen (i.e. CLRWDT times equal two), these two instruc-
tions must be executed to clear the WDT; otherwise, the
WDT may reset the chip because of time-out.
S y s te m C lo c k /8
W DT
O SC
M ask
O p tio n
S e le c t
8 - b it C o u n te r
W D T P r e s c a le r
7 - b it C o u n te r
8 -to -1 M U X
W S 0~W S 2
Watchdog timer
W D T T im e - o u t
Rev. 1.00
11 June 19, 2003

11 Page







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