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PDF HT36F6 Data sheet ( Hoja de datos )
| Número de pieza | HT36F6 | |
| Descripción | Music Synthesizer 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor | |
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HT36F6
Music Synthesizer 8-Bit MCUwww.DataSheet4U.com
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Operating voltage: 2.4V~5.0V
· Operating frequency:
X¢tal: 6MHz~8MHz
ROSC: typ. 6MHz
· Built-in 64K´16-bit (1M-bit) ROM for program/data
shared
· Built-in 8 bit MCU with 208´8 bits RAM
· Two 8 bit programmable timer with 8 stage prescaler
· 20 bidirectional I/O lines
· Four polyphonic synthesizer
· Stereo 16-bit DAC
· Oscillation modes: XTAL/RCOSC
· Low voltage reset
· Eight-level subroutine nesting
· Watchdog timer
· Supports 8-bit table read instruction (TBLP)
· HALT function and wake-up feature reduce power
consumption
· Bit manipulation instructions
· 63 powerful instructions
· All instructions in 1 or 2 machine cycles
· 20/32-pin SOP package
General Description
The HT36F6 is an 8-bit high performance RISC archi-
tecture microcontroller specifically designed for various
music applications. It provides an 8-bit MCU and a
4-channel Wavetable synthesizer. It has a built-in 8-bit
Block Diagram
microprocessor which controls the synthesizer to gen-
erate the melody by setting the special register. A HALT
feature is provided to reduce power consumption.
P A 0~P A 7
P B 0~P B 7
P C 0~P C 3
O SC1
O SC2
RES
6 4 K ´ 1 6 - b it
ROM
8 - B it 2 0 8 ´ 8
M CU RAM
VDD
VSS
VDDA
VSSA
M u ltip lie r /P h a s e
G e n e ra l
1 6 - B it
DAC
LC H
RCH
Rev. 1.00
1 August 15, 2005
1 page  
HT36F6
Function Description
Execution Flow
The system clock for the HT36F6 is derived from either
a crystal or an RC oscillator. The oscillator frequency di-
vided by 2 is the system clock for the MCU and it is inter-
nally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute in one cycle. If an instruction
changes the program counter, two cycles are required
to complete the instruction.
Program Counter - PC
The 13-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are ex-
ecuted and its contents specify a maximum of 8192 ad-
dresses for each bank.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points
to the memory word containing the next instruction
code.
www.DataSheet4U.com
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to retrieve the proper instruction. Other-
wise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Once a control transfer takes place, an additional
dummy cycle is required.
Program ROM
HT36F6 provides 17 address lines WA16~WA0 to read
the Program ROM which is up to 1M bits, and is com-
monly used for the wavetable voice codes and the pro-
gram memory. It provides two address types, one type is
for program ROM, which is addressed by a bank pointer
PF2~PF0 and a 13-bit program counter PC12~PC0;
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
S y s te m C lo c k o f M C U
( S y s te m C lo c k /2 )
PC PC
PC +1
PC +2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
Execution Flow
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Mode
Program Counter
*15 *14 *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Initial Reset
0000000000000000
Timer/Event Counter 0 Overflow PF2 PF1 PF0 0 0 0 0 0 0 0 0 0 1 0 0 0
Timer/Event Counter 1 Overflow PF2 PF1 PF0 0 0 0 0 0 0 0 0 0 1 1 0 0
Skip
Program Counter+2
Loading PCL
PF2 PF1 PF0 *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch
PF2 PF1 PF0 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return From Subroutine
PF2 PF1 PF0 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Note:
*12~*0: Bits of Program Counter
@7~@0: Bits of PCL
#12~#0: Bits of Instruction Code
Program Counter
S12~S0: Bits of Stack Register
@7~@0: Bits of PCL
PF2~PF1: Bits of Bank Register
Rev. 1.00
5 August 15, 2005
5 Page 
· All I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
· The HALT pin will output a high level signal to disable
the external ROM.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a ²warm reset². By examining the TO and PDF
flags, the cause for a chip reset can be determined. The
PDF flag is cleared when there is a system power-up or by
executing the ²CLR WDT² instruction and it is set when a
²HALT² instruction is executed. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that only re-
sets the Program Counter and SP, the others remain in
their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by mask option. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If awakening from an interrupt, two sequences
may occur. If the related interrupts is disabled or the in-
terrupts is enabled but the stack is full, the program will
resume execution at the next instruction. If the interrupt
is enabled and the stack is not full, a regular interrupt re-
sponse takes place.
Once a wake-up event occurs, it takes 1024 tSYS (sys-
tem clock period) to resume to normal operation. In
other words, a dummy cycle period will be inserted after
the wake-up. If the wake-up results from an interrupt ac-
knowledge, the actual interrupt subroutine will be de-
layed by one more cycle. If the wake-up results in next
instruction execution, this will execute immediately after
a dummy period has finished. If an interrupt request flag
is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.
Reset
There are 3 ways in which a reset can occur:
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
set² that just resets the Program Counter and SP, leav-
ing the other circuits to maintain their state. Some regis-
ters remain unchanged during any other reset
conditions. Most registers are reset to the ²initial condi-
tion² when the reset conditions are met. By examining
the PDF and TO flags, the program can distinguish be-
tween different ²chip resets².
HT36F6
TO PDF
RESET Conditiownsww.DataSheet4U.com
0 0 RES reset during power-up
u u RES reset during normal operation
0 1 RES wake-up HALT
1 u WDT time-out during normal operation
1 1 WDT wake-up HALT
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses during system
power up or when the system awakes from a HALT
state.
When a system power-up occurs, the SST delay is
added during the reset period. But when the reset co-
mes from the RES pin, the SST delay is disabled. Any
wake-up from HALT will enable the SST delay.
The functional units chip reset status are shown below.
Program Counter
Interrupt
Prescaler
WDT
Timer Counter (0/1)
Input/output ports
Stack Pointer
000H
Disable
Clear
Clear. After master reset,
WDT begins counting
Off
Input mode
Points to the top of stack
VDD
RES
S S T T im e - o u t
tS S T
C h ip R e s e t
Reset Timing Chart
V DD
RES
H A LT
W DT
RES
Reset Circuit
W DT
T im e - o u t
R eset
O SCI
SST
1 0 -s ta g e
R ip p le C o u n te r
W a rm R e s e t
C o ld
R eset
P o w e r - o n D e te c tin g
Reset Configuration
Rev. 1.00
11 August 15, 2005
11 Page | ||
| Páginas | Total 37 Páginas | |
| PDF Descargar | [ Datasheet HT36F6.PDF ] | |
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