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PDF HYB18H256321BF-12 Data sheet ( Hoja de datos )
| Número de pieza | HYB18H256321BF-12 | |
| Descripción | 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM | |
| Fabricantes | Qimonda AG | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HYB18H256321BF-12 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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September 2007
www.DataSheet4U.com
HYB18H256321BF–11/12/14
HYB18H256321BF–10
256-Mbit GDDR3 Graphics RAM
GDDR3 Graphics RAM
RoHS compliant
Internet Data Sheet
Rev. 0.80
1 page  
2 Configuration
Internet Data Sheet
www.DataSheet4U.com
HYB18H256321BF
256-Mbit GDDR3
FIGURE 1
Ballout 256-Mbit GDDR3 Graphics RAM [Top View, MF = Low ]
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Rev. 0.80, 2007-09
09132007-07EM-7OYI
5
5 Page 
Internet Data Sheet
www.DataSheet4U.com
HYB18H256321BF
256-Mbit GDDR3
3 Functional Description
3.1 Mode Register Set Command (MRS)
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FIGURE 2
Mode Register Set Command
The Mode Register stores the data for controlling the
operation modes of the memory. It programs CAS latency,
test mode, DLL Reset , the value of the Write Latency and the
Burst length. The Mode Register must be written after power
up to operate the SGRAM. During a ModeRegister Set
command the address inputs are sampled and stored in the
Mode Register. The Mode Register content can only be set or
changed when the chip is in Idle state. For non-READ
commands following a Mode Register Set a delay of tMRD
must be met.
The Mode Register Bitmap is supported in two configurations.
The first configuration is intended to support the Mid-Range-
Speed application. The second configuration supports higher
clock cycles for CAS latency and is therefore prepared to
support high-speed application. The selected configuration is
defined by Bit0 of EMRS2.
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Rev. 0.80, 2007-09
09132007-07EM-7OYI
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HYB18H256321BF-12.PDF ] | |
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