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R2023T Schematic ( PDF Datasheet ) - RICOH

Teilenummer R2023T
Beschreibung 2-wire Serial Interface Real Time Clock IC
Hersteller RICOH
Logo RICOH Logo 




Gesamt 30 Seiten
R2023T Datasheet, Funktion
R2023K/T
www.DataSheet4U.com
2-wire Serial Interface Real Time Clock IC
OUTLINE
NO.EA-124-070221
The R2023K/T is a CMOS real-time clock IC connected to the CPU by two signal lines, SCL, SDA, and configured
to perform serial transmission of time and calendar data to the CPU. The periodic interrupt circuit is configured to
generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. The 2 alarm
interrupt circuits generate interrupt signals at preset times. As the oscillation circuit is driven under constant
voltage, fluctuation of the oscillator frequency due to supply voltage is small, and the time keeping current is small
(TYP. 0.45µA at 3V). The oscillation halt sensing circuit can be used to judge the validity of internal data in such
events as power-on; The supply voltage monitoring circuit is configured to record a drop in supply voltage below
two selectable supply voltage monitoring threshold settings. The 32.768kHz clock output function (CMOS output
with control pin) is intended to output sub-clock pulses for the external microcomputer. The oscillation adjustment
circuit is intended to adjust time counts with high precision by correcting deviations in the oscillation frequency of
the crystal oscillator. Since the package for these ICs are TSSOP10G (4.0x2.9x1.0: R2023T) or FFP12
(2.0x2.0x1.0: R2023K), high density mounting of ICs on boards is possible.
FEATURES
Minimum Timekeeping supply voltage TYP:0.66 to 5.5v (Worst: 1.00V to 5.5v); VDD pin
Low power consumption
0.45µA TYP at VDD=3V (1.00µA MAX.)
Two signal lines (SCL, SDA) required for connection to the CPU.
Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days,
and weeks) (in BCD format)
Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month) to
the CPU and provided with an interrupt flag and an interrupt halt
2 alarm interrupt circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and minute
alarm settings)
With Power-on flag to prove that the power supply starts from 0V
32-kHz clock output pin (CMOS push-pull output with control pin)
Supply voltage monitoring circuit with two supply voltage monitoring threshold settings
Automatic identification of leap years up to the year 2099
Selectable 12-hour and 24-hour mode settings
High precision oscillation adjustment circuit
Built-in oscillation stabilization capacitors (CG and CD)
Package TSSOP10G (4.0mm x 2.9mm x 1.0mm: R2023T) FFP12 (2.0mm x 2.0mm x 1.0mm: R2023K)
CMOS process
1






R2023T Datasheet, Funktion
R2023K/T
www.DataSheet4U.com
AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified: VSS=0V,Topt=-40 to +85°C
Input and Output Conditions: VIH=0.8×VDD,VIL=0.2×VDD,VOH=0.8×VDD,VOL=0.2×VDD,CL=50pF
Sym
Item
Condi-
VDD1.7V *1)
-bol
Tions
Min.
Typ.
Max.
Unit
fSCL
tLOW
tHIGH
tHD;STA
tSU;STO
tSU;STA
tSU;DAT
tHD;DAT
tPL;DAT
SCL Clock Frequency
SCL Clock Low Time
SCL Clock High Time
Start Condition Hold Time
Stop Condition Set Up Time
Start Condition Set Up Time
Data Set Up Time
Data Hold Time
SDA “L” Stable Time
After Falling of SCL
400 kHz
1.3 µs
0.6 µs
0.6 µs
0.6 µs
0.6 µs
200 ns
0 ns
0.9 µs
tPZ;DAT
SDA off Stable Time
After Falling of SCL
0.9 µs
tR Rising Time of SCL and SDA
(input)
300 ns
tF Falling Time of SCL and SDA
(input)
300 ns
tSP Spike Width that can be
removed with Input Filter
50 ns
tRCV Recovery Time from Stop
Condition to Start Condition
62
µs
*) For reading/writing timing, see “P.28 Interfacing with the CPU Data Transmission under Special Conditions”.
S Sr P
SCL
tLOW
tHIGH
tHD;STA tSP
SDA(IN)
tHD;STA
tSU;DAT
tHD;DAT
SDA(OUT)
tPL;DAT
S Start Condition
Sr Repeated Start Condition
tPZ;DAT
P Stop Condition
tSU;STA
tSU;STO
6

6 Page









R2023T pdf, datenblatt
R2023K/T
www.DataSheet4U.com
Register Settings
Control Register 1 (ADDRESS Eh)
D7 D6 D5 D4 D3 D2 D1 D0
WALE DALE 12 /24 CLEN2 TEST
CT2
CT1
CT0
(For Writing)
WALE DALE 12 /24 CLEN2 TEST
CT2
CT1
CT0
(For Reading)
0 0 0 0 0 0 0 0 Default Settings *)
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0 volts.
(1) WALE, DALEAlarm_W Enable Bit, Alarm_D Enable Bit
WALE,DALE
Description
0 Disabling the alarm interrupt circuit (under the control of the settings
of the Alarm_W registers and the Alarm_D registers).
1 Enabling the alarm interrupt circuit (under the control of the settings
of the Alarm_W registers and the Alarm_D registers)
(Default)
(2) 12 /24
12 /24-hour Mode Selection Bit
12 /24
Description
0 Selecting the 12-hour mode with a.m. and p.m. indications.
1 Selecting the 24-hour mode
Setting the 12 /24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively.
(Default)
24-hour mode
12-hour mode
24-hour mode
00
12 (AM12)
12
01
01 (AM 1)
13
02
02 (AM 2)
14
03
03 (AM 3)
15
04
04 (AM 4)
16
05
05 (AM 5)
17
06
06 (AM 6)
18
07
07 (AM 7)
19
08
08 (AM 8)
20
09
09 (AM 9)
21
10
10 (AM10)
22
11
11 (AM11)
23
Setting the 12 /24 bit should precede writing time data
12-hour mode
32 (PM12)
21 (PM 1)
22 (PM 2)
23 (PM 3)
24 (PM 4)
25 (PM 5)
26 (PM 6)
27 (PM 7)
28 (PM 8)
29 (PM 9)
30 (PM10)
31 (PM11)
(3) CLEN2
32kHz Clock Output Bit 2
CLEN2
0
1
Description
Enabling the 32-kHz clock circuit
Disabling the 32-kHz clock circuit
(Default)
Setting the CLEN2 bit or the CLEN1 bit (D3 in the control register 2) to 0, and the CLKC pin to high
specifies generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output
from the 32KOUT pin. Conversely, setting both the CLEN1 and CLEN2 bit to 1 or CLKC pin to low
specifies disabling (”L”) such output.
(4) TEST
Test Bit
TEST
Description
0 Normal operation mode.
1 Test mode.
The TEST bit is used only for testing in the factory and should normally be set to 0.
(Default)
12

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