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PDF LM5115A Data sheet ( Hoja de datos )
| Número de pieza | LM5115A | |
| Descripción | Secondary Side Post Regulator/DC-DC Converter with Power-up/Power-down Tracking | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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January 2007
www.DataSheet4U.com
LM5115A
Secondary Side Post Regulator/DC-DC Converter with
Power-up/Power-down Tracking
General Description
The LM5115A controller contains all of the features neces-
sary to produce multiple tracking outputs using the Secondary
Side Post Regulation (SSPR) technique. The SSPR tech-
nique develops a highly efficient and well regulated auxiliary
output from the secondary side switching waveform of an iso-
lated power converter. LM5115A can be also used as a
standalone DC/DC synchronous buck controller (Refer to
Synchronous Buck section). Regulation of the auxiliary
output voltage is achieved by leading edge pulse width mod-
ulation (PWM) of the main channel duty cycle. Leading edge
modulation is compatible with either current mode or voltage
mode control of the main output. The LM5115A drives exter-
nal high-side and low-side NMOS power switches configured
as a synchronous buck regulator. A current sense amplifier
provides overload protection and operates over a wide com-
mon mode input range. Additional features include a low
dropout (LDO) bias regulator, error amplifier, precision refer-
ence, adaptive dead time control of the gate signals and
thermal shutdown.
Features
■ Power-up/Power-down Tracking
■ Self-synchronization to main channel output
■ Leading edge pulse width modulation
■ Valley current Mode control
■ Standalone DC/DC synchronous buck mode
■ Operates from AC or DC input up to 75V
■ Wide 4.5V to 30V bias supply range
■ Wide 0.75V to 13.5V output range.
■ Top and bottom gate drivers sink 2.5A peak
■ Adaptive gate driver dead-time control
■ Wide bandwidth error amplifier (4MHz)
■ Programmable soft-start
■ Thermal shutdown protection
■ TSSOP-16 package
Typical Application Circuit
20207101
FIGURE 1. Simplified Multiple Output Power Converter Utilizing SSPR Technique
© 2007 National Semiconductor Corporation 202071
www.national.com
1 page  
Symbol
Parameter
Conditions
CURRENT LIMIT
Slow ILIMIT Amp Transconductance
Overall Transconductance
Slow ILimit Threshold
VCL = VCS - VVOUT
VOUT = 6V and CO/COMP = 1.5V
Slow ILimit Foldback
VCL = VCS - VVOUT
VOUT = 0V and CO/COMP = 1.5V
Fast ILimit Pull-Down Current
Vds = 2V
Fast ILimit Threshold
VCLNEG Negative Current Limit
CO Clamp Voltage
VOUT = 6V
VCL = VCS - VVOUT to cause LO to shutoff
ICO Pull-Up Current
RAMP GENERATOR
SYNC Input Impedance
SYNC Threshold
End of cycle detection threshold
Free Run Mode Peak Threshold
RAMP peak voltage with dc current
applied to SYNC.
Current Mirror Gain
Ratio of RAMP charge current to SYNC
input current.
Discharge Impedance
LOW-SIDE GATE DRIVER
VOLL
VOHL
LO Low-state Output Voltage
LO High-state Output Voltage
LO Rise Time
LO Fall Time
IOHL Peak LO Source Current
IOLL Peak LO Sink Current
HIGH-SIDE GATE DRIVER
ILO = 100mA
ILO = -100mA, VOHL = VCC -VLO
CLOAD = 1000pF
CLOAD = 1000pF
VLO = 0V
VLO = 12V
VOLH
VOHH
HO Low-state Output Voltage
HO High-state Output Voltage
HO Rise Time
HO High-side Fall Time
IOHH Peak HO Source Current
IOLH Peak HO Sink Current
SWITCHING CHARACTERISITCS
IHO = 100mA
IHO = -100mA, VOHH = VHB –VHO
CLOAD = 1000pF
CLOAD = 1000pF
VHO = 0V
VHO = 12V
LO Fall to HO Rise Delay
HO Fall to LO Rise Delay
SYNC Fall to HO Fall Delay
SYNC Rise to LO Fall Delay
CLOAD = 0
CLOAD = 0
CLOAD = 0
CLOAD = 0
Min
39
34
5.5
2.7
Typ Max Units
www.DataSheet4U.com
5 mA / V
90 mA / V
45 51
mV
39 46
mV
45
60
-17
6 6.5
15
mA
mV
mV
V
µA
2.5
20
2.35
3.3
100
0.15 0.5
0.35 0.8
15
12
2
2.5
kΩ
µA
V
A/A
Ω
V
V
ns
ns
A
A
0.15 0.5
0.35 0.8
15
12
2
2.5
V
V
ns
ns
A
A
40 ns
50 ns
120 ns
80 ns
5 www.national.com
5 Page 
www.DataSheet4U.com
FIGURE 3. Line Feed-Forward Waveforms
20207113
The recommended SYNC input current range is 50µA to
150µA. The SYNC pin resistor (RSYNC) should be selected to
set the SYNC current (ISYNC) to 150µA with the maximum
phase signal amplitude, VPHASE(max). This will guarantee that
ISYNC stays within the recommended range over a 3:1 change
in phase signal amplitude. The SYNC pin resistor is therefore:
RSYNC = (VPHASE(max) / 150µA) - 2.5kΩ
Once ISYNC has been established by selecting RSYNC, the
RAMP signal slope/amplitude may be programmed by se-
lecting the proper RAMP pin capacitor value. The RAMP
signal slope should be selected to provide adequate slope
compensation for the Valley current mode control scheme
(Please refer to the Valley current mode section). The rec-
ommended peak amplitude of the ramp waveform is 1.75V.
Error Amplifier and Soft-Start (FB,
CO, COMP & TRK/SS)
An internal wide bandwidth error amplifier is provided within
the LM5115A for voltage feedback to the PWM controller. The
amplifier’s inverting input is connected to the FB pin. The out-
put of the auxiliary converter is regulated by connecting a
voltage setting resistor divider between the output and the FB
pin. Loop compensation networks are connected between the
FB pin and the error amplifier output (COMP). The amplifier
has two non-inverting inputs. The first non-inverting input
connects to a 0.75V bandgap reference while The second
non-inverting input connects to the TRK/SS pin and it has 15
µA pull-up current source. The TRK/SS pin can be tied to an
external resistor divider from the master output for tracking,
or it can be tied to a capacitor for soft-start . TRK/SS is the
reference input to the amplifier when the voltage applied to
the pin is < 0.75V. For higher inputs, the internal reference
controls the amplifier. When the VCC voltage is below the
UVLO threshold, the TRK/SS pin is discharged to ground.
When VCC rises and exceeds the positive going UVLO
threshold (4.25V), the TRK/SS pin is released and allowed to
rise. If an external capacitor is connected to the TRK/SS pin,
it will be charged by the internal 15uA pull-up current source
to gradually increase the non-inverting input of the error am-
plifier to 0.75V. During start-up, the output of the LM5115A
converter will follow the following equation:
VOUT(t) = VOUT(final) x15 µA x t /(.75 Vx Css )
Where
Css = external Soft-Start capacitor
VOUT(final) = regulator output set point
Pull-up current for the error amplifier output is provided by an
internal 300µA current source. The PWM threshold signal at
the COMP pin can be controlled by either the open drain error
amplifier or the open drain current amplifier connected
through the CO pin to COMP. Since the internal error amplifier
is configured as an open drain output it can be disabled by
connecting FB to ground. The current sense amplifier and
current limiting function will be described in a later section.
Power-up/Power-downTracking
The LM5115A can track the output of a master power supply
during soft start by connecting a resistor divider to the TRACK
pin (Figure 4). Therefore, the output voltage slew rate of the
LM5115A will be controlled by the master supply for loads that
require precise sequencing. In order to track properly the out-
put voltage of the LM5115A must be lower than the output
voltage of the master supply.
One way to use the tracking feature is to design the tracking
resistor divider so that the master supply output voltage
(VOUT1) and the LM5115A output voltage (VOUT2) both rise
together and reach their target values at the same time. For
this case, the equation governing the values of the tracking
divider resistors RT1 and RT2 is:
A value of 10kΩ (1%) is recommended for RT2 as a good
compromise between high precision and low quiescent cur-
rent through the divider. If the master supply voltage was 3.3V
and the LM5115A output voltage was 2.5 V, then the value of
RT1 needed to give the two supplies identical soft start times
would be 2.94 kΩ (1%). The timing diagram and waveforms
for the equal soft start time configuration are shown in Figure
5 and Figure 6.
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| PDF Descargar | [ Datasheet LM5115A.PDF ] | |
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