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LC863424A Schematic ( PDF Datasheet ) - Sanyo Semicon Device
| Teilenummer | LC863424A |
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| Beschreibung | 8-Bit Single-Chip Microcontroller | |
| Hersteller | Sanyo Semicon Device | |
| Logo |  |
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Gesamt 19 Seiten 
Ordering number : ENN*6846
CMOS IC
LC863432A/28A/24A/20A/16A
8-Bit Single-Chip Microcontroller
Preliminary
Overview
The LC863432/28/24/20/16A are 8-bit single chip microcontrollers with the following on-chip functional blocks:
- CPU : Operable at a minimum bus cycle time of 0.424µs
- On-chip ROM capacity
Program ROM : 32K/28K/24K/20K/16K bytes
CGROM : 16K bytes
- On-chip RAM capacity : 512 bytes
- OSD RAM : 352 × 9 bits
- Closed-Caption TV controller and the on-screen display controller
- Closed-Caption data slicer
- Four channels × 6-bit AD Converter
- Three channels × 7-bit PWM
- 16-bit timer/counter, 14-bit base timer
- IIC-bus compliant serial interface circuit (Multi-master type)
- ROM correction function
- 11-source 8-vectored interrupt system
- Integrated system clock generator and display clock generator
Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators
TV control and the Closed Caption function
All of the above functions are fabricated on a single chip.
Note : This product includes the IIC bus interface circuit. If you intend to use the IIC bus interface, please
notify us of this in advance of our receiving your program ROM code order.
Purchase of SANYO IIC components conveys a license under the Philips IIC Patents Rights to use these
components in an IIC system, provided that the system conforms to the IIC Standard Specification as
defined by Philips.
Trademarks
IIC is a trademark of Philips Corporation.
Ver.1.01
00000
D2700 RM (IM) Shindo No.6846-1/19
 
Pin Assignment
LC863432A/28A/24A/20A/16A
P10/SDA0
P11/SCLK0
P12/SDA1
P13/SCLK1
VSS
XT1
XT2
VDD
P04/AN4
P05/AN5
P06/AN6
P07/AN7
RES
FILT
CVIN
P30
VS
HS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Package Dimension
(unit : mm)
3129
36 P03
35 P02
34 P01
33 P00
32 P17
31 P16/PWM3
30 P15/PWM2
29 P14/PWM1
28 P73/INT3/T0IN
27 P72/INT2/T0IN
26 P71/INT1
25 P70/INT0
24 P32
23 P31
22 BL
21 B
20 G
19 R
SANYO : MFP-36S
No.6846-6/19
6 Page 
LC863432A/28A/24A/20A/16A
4. IIC Input/Output Conditions at Ta=-10°C to +70°C, VSS=0V
Parameter
Symbol
Standard
min. max.
SCL Frequency
BUS free time between stop - start
fSCL
tBUF
0 100
4.7 -
HOLD time of start, restart condition
tHD;STA
4.0
-
L time of SCL
tLOW 4.7 -
H time of SCL
tHIGH 4.0 -
Set-up time of restart condition
tSU;STA
4.7
-
HOLD time of SDA
tHD;DAT
0
-
Set-up time of SDA
Rising time of SDA, SCL
Falling time of SDA, SCL
Set-up time of stop condition
tSU;DAT
tR
tF
tSU;STO
250 -
- 1000
- 300
4.0 -
Refer to figure 8
(Note) Cb : Total capacitance of all BUS (unit : pF)
High speed
min. max.
0 400
1.3 -
0.6 -
1.3 -
0.6 -
0.6 -
0 0.9
100 -
20+0.1Cb 300
20+0.1Cb 300
0.6 -
unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
5. Pulse Input Conditions at Ta=-10°C to +70°C, VSS=0V
Parameter Symbol
Pins
Conditions
Ratings
unit
VDD[V] min. typ. max.
High/low level tPIH(1) •INT0, INT1
pulse width tPIL(1) •INT2/T0IN
•Interrupt acceptable 4.5 to 5.5
•Timer0-countable
1
tCYC
tPIH(2)
tPIL(2)
INT3/T0IN
(1 tCYC is
selected for noise
rejection clock.)
•Interrupt acceptable
•Timer0-countable
4.5 to 5.5
2
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
INT3/T0IN
(16 tCYC is
selected for noise
rejection clock.)
INT3/T0IN
(64 tCYC is
selected for noise
rejection clock.)
RES
•Interrupt acceptable
•Timer0-countable
•Interrupt acceptable
•Timer0-countable
Reset acceptable
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
32
128
200
µs
tPIH(6) HS , VS
tPIL(6)
•Display position
controllable (Note)
•The active edge of
4.5 to 5.5
8
HS and VS must
be apart at least
1 tCYC.
•Refer to figure 6.
Rising/falling tTHL
time tTLH
HS
Refer to figure 6.
4.5 to 5.5
500 ns
No.6846-12/19
12 Page | ||
| Seiten | Gesamt 19 Seiten | |
| PDF Download | [ LC863424A Schematic.PDF ] | |
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