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PDF CYDC128B16 Data sheet ( Hoja de datos )
| Número de pieza | CYDC128B16 | |
| Descripción | 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CYDC256B16, CYDC128B16,
CYDC064B16,wCwwY.DDaCtaS1h2ee8t4BU.c0o8m,
CYDC064B08
1.8V 4k/8k/16k x 16 and 8k/16k x 8
ConsuMoBL Dual-Port Static RAM
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• 4/8/16k × 16 and 8/16k × 8 organization
• High-speed access: 40 ns
• Ultra Low operating power
— Active: ICC = 15 mA (typical) at 55 ns
— Active: ICC = 25 mA (typical) at 40 ns
— Standby: ISB3 = 2 µA (typical)
• Port-independent 1.8V, 2.5V, and 3.0V I/Os
• Lead (Pb)-free 14 x 14 x 1.4 mm 100-pin TQFP Package
• Full asynchronous operation
• Pin select for Master or Slave
• Expandable data bus to 32 bits with Master/Slave chip
select when using more than one device
• On-chip arbitration logic
• On-chip semaphore logic
• Input Read Registers and Output Drive Registers
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Commercial and industrial temperature ranges
Selection Guide for VCC = 1.8V
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-40
Port I/O Voltages (P1-P2)
1.8V-1.8V
Maximum Access Time
40
Typical Operating Current
25
Typical Standby Current for ISB1
Typical Standby Current for ISB3
2
2
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-55
1.8V-1.8V
55
15
2
2
Unit
ns
mA
µA
µA
Selection Guide for VCC = 2.5V
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-40
Port I/O Voltages (P1-P2)
2.5V-2.5V
Maximum Access Time
40
Typical Operating Current
39
Typical Standby Current for ISB1
Typical Standby Current for ISB3
6
4
Selection Guide for VCC = 3.0V
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-40
Port I/O Voltages (P1-P2)
3.0V-3.0V
Maximum Access Time
40
Typical Operating Current
49
Typical Standby Current for ISB1
Typical Standby Current for ISB3
7
6
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-55
2.5V-2.5V
55
28
6
4
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-55
3.0V-3.0V
55
42
7
6
Unit
ns
mA
µA
µA
Unit
ns
mA
µA
µA
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-01638 Rev. *E
Revised January 25, 2007
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CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
wCwwY.DDaCtaS0he6e4t4BU.c0o8m
Pin Definitions
Left Port
Right Port
CEL
CER
R/WL
R/WR
OEL
OER
A0L–A13L
A0R–A13R
I/O0L–I/O15L
I/O0R–I/O15R
SEML
SEMR
UBL
UBR
LBL LBR
INTL
INTR
BUSYL
BUSYR
IRR0, IRR1
ODR0-ODR4
SFEN
M/S
VCC
GND
VDDIOL
VDDIOR
NC
Description
Chip Enable
Read/Write Enable
Output Enable
Address (A0–A11 for 4k devices; A0–A12 for 8k devices; A0–A13 for 16k devices).
Data Bus Input/Output for x16 devices; I/O0–I/O7 for x8 devices.
Semaphore Enable
Upper Byte Select (I/O8–I/O15 for x16 devices; Not applicable for x8 devices).
Lower Byte Select (I/O0–I/O7 for x16 devices; Not applicable for x8 devices).
Interrupt Flag
Busy Flag
Input Read Register for CYDC064B16, CYDC064B08, CYDC128B16.
A13L, A13R for CYDC256B16 and CYDC128B08 devices.
Output Drive Register; These outputs are Open Drain.
Special Function Enable
Master or Slave Select
Core Power
Ground
Left Port I/O Voltage
Right Port I/O Voltage
No Connect. Leave this pin Unconnected.
Functional Description
The CYDC256B16, CYDC128B16, CYDC064B16,
CYDC128B08, CYDC064B08 are low-power CMOS 4k,
8k,16k x 16, and 8/16k x 8 dual-port static RAMs. Arbitration
schemes are included on the devices to handle situations
when multiple processors access the same piece of data. Two
ports are provided, permitting independent, asynchronous
access for reads and writes to any location in memory. The
devices can be utilized as standalone 16-bit dual-port static
RAMs or multiple devices can be combined in order to function
as a 32-bit or wider master/slave dual-port static RAM. An M/S
pin is provided for implementing 32-bit or wider memory appli-
cations without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt flag
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a Chip
Enable (CE) pin.
The CYDC256B16, CYDC128B16, CYDC064B16,
CYDC128B08, CYDC064B08 are available in 100-pin TQFP
packages.
Power Supply
The core voltage (VCC) can be 1.8V, 2.5V or 3.0V, as long as
it is lower than or equal to the I/O voltage.
Each port can operate on independent I/O voltages. This is
determined by what is connected to the VDDIOL and VDDIOR
pins. The supported I/O standards are 1.8V/2.5V LVCMOS
and 3.0V LVTTL.
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summa-
rized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port tDDD after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE is asserted. If the user wishes to access a semaphore flag,
Document #: 001-01638 Rev. *E
Page 5 of 26
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CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
wCwwY.DDaCtaS0he6e4t4BU.c0o8m
Electrical Characteristics for VCC = 2.5V Over the Operating Range
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
-40
Parameter
Description
P1 I/O P2 I/O
Voltage Voltage Min. Typ. Max.
VOH
VOL
VOL ODR
Output HIGH Voltage (IOH = –2 mA)
Output HIGH Voltage (IOH = –2 mA)
Output LOW Voltage (IOL = 2 mA)
Output LOW Voltage (IOL = 2 mA)
ODR Output LOW Voltage (IOL = 8 mA)
2.5V (any port)
3.0V (any port)
2.5V (any port)
3.0V (any port)
2.5V (any port)
3.0V (any port)
2.0
2.1
0.4
0.4
0.2
0.2
VIH Input HIGH Voltage
2.5V (any port) 1.7
VDDIO
+ 0.3
3.0V (any port) 2.0
VDDIO
+ 0.2
VIL Input LOW Voltage
2.5V (any port)
3.0V (any port)
–0.3
–0.2
0.6
0.7
IOZ Output Leakage Current
2.5V
3.0V
2.5V
3.0V
–1
–1
1
1
ICEX ODR ODR Output Leakage Current.
VOUT = VCC
2.5V
3.0V
2.5V
3.0V
–1
–1
1
1
IIX Input Leakage Current
2.5V
3.0V
2.5V
3.0V
–1
–1
1
1
ICC
Operating Current (VCC = Max., Ind. 2.5V
2.5V
IOUT = 0 mA) Outputs Disabled
ISB1 Standby Current (Both Ports TTL Ind. 2.5V 2.5V
Level) CEL and CER ≥ VCC – 0.2,
SEM L= SEMR = VCC – 0.2, f=fMAX
ISB2 Standby Current (One Port TTL Ind. 2.5V 2.5V
Level) CEL | CER ≥ VIH, f = fMAX
ISB3
Standby Current (Both Ports
Ind. 2.5V 2.5V
CMOS Level) CEL & CER ≥
VCC − 0.2V, SEML and SEMR >
VCC – 0.2V, f = 0
ISB4
Standby Current (One Port CMOS Ind. 2.5V
Level) CEL | CER ≥ VIH, f = fMAX[25]
2.5V
39 55
68
21 30
46
21 30
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
-55
Min.
2.0
2.1
1.7
2.0
–0.3
–0.2
–1
–1
–1
–1
–1
–1
Typ.
28
Max. Unit
V
V
0.4 V
0.4 V
0.2 V
0.2 V
VDDIO V
+ 0.3
VDDIO V
+ 0.2
0.6 V
0.7 V
1 µA
1 µA
1 µA
1 µA
1 µA
1 µA
40 mA
6 8 µA
18 25 mA
4 6 µA
18 25 mA
Document #: 001-01638 Rev. *E
Page 11 of 26
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| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet CYDC128B16.PDF ] | |
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