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LM5025A Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer LM5025A
Beschreibung Active Clamp Voltage Mode PWM Controller
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 16 Seiten
LM5025A Datasheet, Funktion
December 2004
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LM5025A
Active Clamp Voltage Mode PWM Controller
General Description
The LM5025A is a functional variant of the LM5025 active
clamp PWM controller. The functional differences of the
LM5025A are: The CS1 and CS2 current limit thresholds
have been increased to 0.5V. The internal CS2 filter dis-
charge device has been disabled and no longer operates
each clock cycle. The internal VCC and VREF regulators
continue to operate when the line UVLO pin is below thresh-
old.
The LM5025A PWM controller contains all of the features
necessary to implement power converters utilizing the Active
Clamp / Reset technique. With the active clamp technique,
higher efficiencies and greater power densities can be real-
ized compared to conventional catch winding or RDC clamp
/ reset techniques. Two control outputs are provided, the
main power switch control (OUT_A) and the active clamp
switch control (OUT_B). The two internal compound gate
drivers parallel both MOS and Bipolar devices, providing
superior gate drive characteristics. This controller is de-
signed for high-speed operation including an oscillator fre-
quency range up to 1MHz and total PWM and current sense
propagation delays less than 100ns. The LM5025A includes
a high-voltage start-up regulator that operates over a wide
input range of 13V to 90V. Additional features include: Line
Under Voltage Lockout (UVLO), softstart, oscillator UP/
DOWN sync capability, precision reference and thermal
shutdown.
Features
n Internal Start-up Bias Regulator
n 3A Compound Main Gate Driver
n Programmable Line Under-Voltage Lockout (UVLO) with
Adjustable Hysteresis
n Voltage Mode Control with Feed-Forward
n Adjustable Dual Mode Over-Current Protection
n Programmable Overlap or Deadtime between the Main
and Active Clamp Outputs
n Volt x Second Clamp
n Programmable Soft-start
n Leading Edge Blanking
n Single Resistor Programmable Oscillator
n Oscillator UP / DOWN Sync Capability
n Precision 5V Reference
n Thermal Shutdown
Packages
n TSSOP-16
n LLP-16 (5x5 mm) Thermally Enhanced
Typical Application Circuit
Simplified Active Clamp Forward Power Converter
20107401
© 2004 National Semiconductor Corporation DS201074
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LM5025A Datasheet, Funktion
Electrical Characteristics (Continued)
Specifications with standard typeface are for TJ = 25˚C, and those with boldface type apply over fuwllwOwp.DeraattainSgheJeutn4cUt.icoonm
Temperature range. VIN = 48V, VCC = 10V, RT = 31.3k, RSET = 27.4k) unless otherwise stated (Note 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CS2 Sink Impedance CS2 = 0.6V
55 85
(Post Fault Discharge)
CS1 and CS2
CS = CS Threshold -
1 µA
Leakage Current
100mV
Soft-Start
Soft-start Current
17 22 27 µA
Source Normal
Soft-start Current
0.5 1 1.5 µA
Source following a
CS2 event
Oscillator
Frequency1
Frequency2
TA = 25˚C
TJ = Tlow to Thigh
RT = 10.4K
180 200 220 kHz
175 225
510 580 650 kHz
Sync threshold
2V
Min Sync Pulse Width
100 ns
Sync Frequency
160 kHz
Range
PWM Comparator
Delay to Output
COMP step 5V to 0V
40 ns
Time to onset of OUT_A
transition low
Duty Cycle Range
0 80 %
COMP to PWM Offset
0.7 1 1.3 V
COMP Open Circuit
4.3 5.9 V
Voltage
COMP Short Circuit
COMP = 0V
0.6 1 1.4 mA
Current
Volt x Second Clamp
Ramp Clamp Level
Delta RAMP measured
2.4
2.5 2.6 V
from onset of OUT_A to
Ramp peak.
COMP = 5V
UVLO Shutdown
Undervoltage
2.44
2.5
2.56
V
Shutdown Threshold
Undervoltage
16 20 24 µA
Shutdown Hysteresis
Output Section
OUT_A High
MOS Device @ Iout =
5 10
Saturation
-10mA,
OUTPUT_A Peak
Bipolar Device @ Vcc/2
3A
Current Sink
OUT_A Low
MOS Device @ Iout =
6 9
Saturation
10mA,
OUTPUT_A Rise Time
OUTPUT_A Fall Time
OUT_B High
Cgate = 2.2nF
Cgate = 2.2nF
MOS Device @ Iout =
20 ns
15 ns
10 20
Saturation
-10mA,
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LM5025A pdf, datenblatt
Current Limit (Continued)
the PWM comparator will produce the first output pulse at
OUT_A. After the first pulse occurs, the softstart current
source will revert to the normal 20µA level. Fully discharging
and then slowly charging the SS capacitor protects a con-
tinuously over-loaded converter with a low duty cycle hiccup
mode.
These two modes of over-current protection allow the user
great flexibility to configure the system behavior in over-load
conditions. If it is desired for the system to act as a current
source during an over-load, then the CS1 cycle-by-cycle
current limiting should be used. In this case the current
sense signal should be applied to the CS1 input and the CS2
input should be grounded. If during an overload condition it is
desired for the system to briefly shutdown, followed by soft-
start retry, then the CS2 hiccup current limiting mode should
be used. In this case the current sense signal should be
applied to the CS2 input and the CS1 input should be
grounded. This shutdown / soft-start retry will repeat indefi-
nitely while the over-load condition remains. The hiccup
mode will greatly reduce the thermal stresses to the system
during heavy overloads. The cycle-by-cycle mode will have
higher system thermal dissipations during heavy overloads,
but provides the advantage of continuous operation for short
duration overload conditions.
It is possible to utilize both over-current modes concurrently,
whereby slight overload conditions activate the CS1 cycle-
by-cycle mode while more severe overloading activates the
CS2 hiccup mode. Generally the CS1 input will always be
configured to monitor the main switch FET current each
cycle. The CS2 input can be configured in several different
ways depending upon the system requirements.
a) The CS2 input can also be set to monitor the main switch
FET current except scaled to a higher threshold than CS1
b) An external over-current timer can be configured which
trips after a pre-determined ovwerw-cwur.DreanttatSimheee, td4rUiv.cinogmthe
CS2 input high, initiating a hiccup event.
c) In a closed loop voltage regulaton system, the COMP
input will rise to saturation when the cycle-by-cycle current
limit is active. An external filter/delay timer and voltage di-
vider can be configured between the COMP pin and the CS2
pin to scale and delay the COMP voltage. If the CS2 pin
voltage reaches 0.5V a hiccup event will initiate.
A small RC filter, located near the controller, is recom-
mended for each of the CS pins. The CS1 input has an
internal FET which discharges the current sense filter ca-
pacitor at the conclusion of every cycle, to improve dynamic
performance. This same FET remains on an additional 50ns
at the start of each main switch cycle to attenuate the leading
edge spike in the current sense signal. The CS2 discharge
FET only operates following a CS2 event, UVLO and thermal
shutdown.
The LM5025A CS comparators are very fast and may re-
spond to short duration noise pulses. Layout considerations
are critical for the current sense filter and sense resistor. The
capacitor associated with the CS filter must be placed very
close to the device and connected directly to the pins of the
IC (CS and GND). If a current sense transformer is used,
both leads of the transformer secondary should be routed to
the filter network , which should be located close to the IC. If
a sense resistor in the source of the main switch MOSFET is
used for current sensing, a low inductance type of resistor is
required. When designing with a current sense resistor, all of
the noise sensitive low power ground connections should be
connected together near the IC GND and a single connec-
tion should be made to the power ground (sense resistor
ground point).
Oscillator and Sync Capability
The LM5025A oscillator is set by a single external resistor
connected between the RT pin and GND. To set a desired
oscillator frequency (F), the necessary RT resistor can be
calculated from:
RT = (5725/F)1.026
where F is in kHz and RT in k.
The RT resistor should be located very close to the device
and connected directly to the pins of the IC (RT and GND).
A unique feature of LM5025A is the ability to synchronize the
oscillator to an external clock with a frequency that is either
higher or lower than the frequency of the internal oscillator.
The lower frequency sync frequency range is 80% of the free
running internal oscillator frequency. There is no constraint
on the maximum SYNC frequency. A minimum pulse width of
100ns is required for the synchronization clock . If the syn-
20107414
chronization feature is not required, the SYNC pin should be
connected to GND to prevent any abnormal interference .
The internal oscillator can be completely disabled by con-
necting the RT pin to REF. Once disabled, the sync signal
will act directly as the master clock for the controller. Both the
frequency and the maximum duty cycle of the PWM control-
ler can be controlled by the SYNC signal (within the limita-
tions of the Volt x Second Clamp). The maximum duty cycle
(D) will be (1-D) of the SYNC signal.
Feed-Forward Ramp
An external resistor (RFF) and capacitor (CFF) connected to
VIN and GND are required to create the PWM ramp signal.
The slope of the signal at the RAMP pin will vary in propor-
tion to the input line voltage. This varying slope provides line
feedforward information necessary to improve line transient
response with voltage mode control. The RAMP signal is
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