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PDF IS41LV8205A Data sheet ( Hoja de datos )

Número de pieza IS41LV8205A
Descripción 2M x 8 (16-MBIT) DYNAMIC RAM
Fabricantes Integrated Silicon Solution 
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No Preview Available ! IS41LV8205A Hoja de datos, Descripción, Manual

IS41LV8205A
2M x 8 (16-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
ISSI®
www.DataSheet4U.com
FEBRUARY 2005
FEATURES
• Fast Page Mode Access Cycle
• TTL compatible inputs and outputs
• Refresh Interval:
-- 2,048 cycles/32 ms
• Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden
• Single power supply: 3.3V ± 10%
• Byte Write and Byte Read operation via two CAS
• Lead-free available
PRODUCT SERIES OVERVIEW
Part No.
IS41LV8205A
Refresh
2K
Voltage
3.3V ± 10%
PIN CONFIGURATION
28 Pin SOJ
DESCRIPTION
The ISSI IS41LV8205A is 2,097,152 x 8-bit high-perfor-
mance CMOS Dynamic Random Access Memory. The
Fast Page Mode allows 2,048 random accesses within a
single row with access cycle time as short as 20 ns per 4-
bit word.
These features make the IS41LV8205A ideally suited for
high-bandwidth graphics, digital signal processing, high-
performance computing systems, and peripheral
applications.
The IS41LV8205A is packaged in 28-pin 300-mil SOJ with
JEDEC standard pinouts.
KEY TIMING PARAMETERS
Parameter
RAS Access Time (tRAC)
CAS Access Time (tCAC)
Column Address Access Time (tAA)
Fast Page Mode Cycle Time (tPC)
Read/Write Cycle Time (tRC)
-50
50
14
25
20
85
-60 Unit
60 ns
15 ns
30 ns
25 ns
104 ns
VDD
I/O0
I/O1
I/O2
I/O3
WE
RAS
NC
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 GND
27 I/O7
26 I/O6
25 I/O5
24 I/O4
23 CAS
22 OE
21 A9
20 A8
19 A7
18 A6
17 A5
16 A4
15 GND
PIN DESCRIPTIONS
A0-A10
I/O0-7
WE
OE
RAS
CAS
VDD
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
02/01/05
1

1 page




IS41LV8205A pdf
IS41LV8205A
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
ISSI ®
www.DataSheet4U.com
Symbol Parameter
Test Condition
VDD Speed Min. Max. Unit
IIL Input Leakage Current Any input 0V VIN VDD
Other inputs not under test = 0V
–5 5 µA
IIO
Output Leakage Current
Output is disabled (Hi-Z)
0V VOUT VDD
–5 5 µA
VOH Output High Voltage Level IOH = –5.0 mA, VDD = 5V
IOH = –2.0 mA, VDD = 3.3V
2.4 — V
VOL Output Low Voltage Level IOL = 4.2 mA, VDD = 5V
IOL = 2 mA, VDD = 3.3V
— 0.4 V
ICC1 Standby Current: TTL
RAS, CAS VIH
3.3V
— 1 mA
ICC2 Standby Current: CMOS RAS, CAS VDD – 0.2V
3.3V
— 1 mA
ICC3 Operating Current:
RAS, CAS,
Random Read/Write(2,3)
Address Cycling, tRC = tRC (min.)
Average Power Supply Current
-50 — 150 mA
-60 — 140
ICC4 Operating Current:
RAS= VIL, CAS VIH
Fast Page Mode(2,3,4)
tRC = tRC (min.)
Average Power Supply Current
ICC5 Refresh Current:
RAS-Only(2,3)
RAS Cycling, CAS VIH
tRC = tRC (min.)
Average Power Supply Current
ICC6 Refresh Current:
RAS, CAS Cycling
CBR(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
-50 — 150 mA
-60 — 140
-50 — 150 mA
-60 — 140
-50 — 150 mA
-60 — 140
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each Fast Page cycle.
5. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
02/01/05
5

5 Page





IS41LV8205A arduino
IS41LV8205A
EARLY WRITE CYCLE (OE = DON'T CARE)
RAS
tCRP
CAS
tASR
ADDRESS
Row
WE
I/O
tRAS
tRC
tRCD
tCSH
tRSH
tCAS tCLCH
tRAD
tRAH
tASC
tAR
tRAL
tCAH
tACH
Column
tWCR
tWCS
tCWL
tRWL
tWCH
tWP
tDHR
tDS
tDH
Valid Data
ISSI ®
www.DataSheet4U.com
tRP
Row
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
02/01/05
11

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