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LC8220 Schematic ( PDF Datasheet ) - Sanyo Semicon Device

Teilenummer LC8220
Beschreibung JPEG Still Color Image Compression/Decompression LSI
Hersteller Sanyo Semicon Device
Logo Sanyo Semicon Device Logo 




Gesamt 13 Seiten
LC8220 Datasheet, Funktion
Ordering number : EN*4909A
Preliminaly
CMOS LSI
LC8220
JPEG Still Color Image
Compression/Decompression LSI
Overview
The LC8220 JPEG LSI implements digital still image
compression and decompression conforming to the JPEG
(Joint Photographic Expert Group) standard. The LC8220
includes the baseline system of the ISO 10918 (JPEG)
standard, and requires no external components to construct
an application that performs JPEG compliant
compression/decompression.
Features
• Conforms to the ISO 10918-1 baseline system
• Four quantization tables and four Huffman tables (two
for AC and two for DC) are built in.
• Hardware support for JPEG marker codes
• Built-in bidirectional YUV - RGB converter
• Many color component sampling ratios are supported.
(e.g., YUV 4:1:1 and YMCK 1:1:1:1, etc.)
• Level shift function that can be defined for each
component
• Built-in dual buffers for reduced data transfer load
• Bus sizing function that allows direct connection to 8-,
16-, and 32-bit busses
• Endian control function
• Three independent data buses
Package Dimensions
unit: mm
3153A-QFP160
[LC8220]
SANYO: QFP160
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
32896HA (OT)/D1694TH (OT) No. 4909-1/13






LC8220 Datasheet, Funktion
LC8220
Specifications
Absolute Maximum Ratings at Ta = 25°C, GND = 0 V
Parameter
Maximum supply voltage
I/O voltages
Operating temperature
Storage temperature
Soldering temperature
Symbol
VDD max
VI, VO
Topr
Tstg
Conditions
Hand soldering: 3 seconds
Reflow soldering: 10 seconds
Ratings
–0.3 to +7.0
–0.3 to VDD + 0.3
–30 to +70
–55 to +125
350
235
Unit
V
V
°C
°C
°C
°C
Allowable Operating Ranges at Ta = –30 to +70°C, GND = 0 V
Parameter
Supply voltage
Input voltage
Symbol
VDD
VIN
Conditions
min typ max Unit
4.5 5.5 V
0
VDD
V
DC Characteristics at Ta = –30 to +70°C, VDD = 4.5 to 5.5 V, GND = 0 V
Parameter
Input high level voltage
Input low level voltage
Input leakage current
Output high level voltage
Output low level voltage
Output leakage current
Oscillator frequency
Current drain
Symbol
VIH
VIL
IL
VOH
VOL
IOZ
fOSC
IDD
Conditions
TTL compatible: CTLCS, CTLRD, CTLWR, CPUCTL,
CTLSIZE, CTLA7 to CTLA0, CLKSEL, RESET, TEST,
CTLD15 to CTLD0
TTL compatible: CPUPX, PXCS, PXRD, PXWR,
PXD31 to PXD0, PXRLS, PXSIZE0
PXSIZE1, CDCS, CDRD, CDWR, CDRLS, CDFLSH,
CPUCD, CDSIZE, CDD15 to CDD0
IOH = –3 mA, TTL compatible: CTLRDY, CTLERR,
CTLINT, TESTOUT, CTLD15 to CTLD0, PXRDY,
PXINT, PXEND, PXD31 to PXD0, CDRDY, CDINT,
CDEND, CDD15 to CDD0
IOH = –3 mA, TTL compatible: CTLRDY, CTLERR,
CTLINT, TESTOUT, CTLD15 to CTLD0, PXRDY,
PXINT, PXEND, PXD31 to PXD0, CDRDY, CDINT,
CDEND, CDD15 to CDD0
For high impedance outputs: CTLD15 to CTLD0,
PXD31 to PXD0, CDD15 to CDD0
CLK
VDD = 5.0 V
min
2.2
–10
VDD – 2.1
–10
typ
145
max
0.8
+10
Unit
V
V
µA
V
0.4 V
+10
16.67
µA
MHz
mA
No. 4909-6/13

6 Page









LC8220 pdf, datenblatt
Control Bus Write Cycle
LC8220
Control Bus Register Write Cycle (type 1)
Control Bus Register Write Cycle (type 2)
Item
t1 Write signal assert setup time (referenced to CLK)
t2 Write signal assert hold time (referenced to CLK)
t3 Chip select stabilization time (referenced to the write signal)
t4 Chip select hold time (referenced to the write signal)
t5 Write cycle selection signal stabilization time (referenced to the write signal)
t6 Write cycle selection signal hold time (referenced to the write signal)
t7 Address stabilization time (referenced to the write signal)
t8 Address hold time (referenced to the write signal)
t9 Ready signal response delay time (referenced to the write signal)
t10 Ready signal release delay time (referenced to the write signal)
t11 Write signal negate setup time (referenced to CLK)
t12 Write signal negate hold time (referenced to CLK)
t13 Data setup time (referenced to the ready signal)
t14 Data hold time (referenced to the ready signal)
T Clock period
Minimum
12
15
10
15
10
10
0
5
5
15
60
20
60
Maximum
T + t1 + 24
t11 + 32
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
No. 4909-12/13

12 Page





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