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AD9776A Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9776A
Beschreibung Dual 12-/14-/16-Bit 1 GSPS Digital-to-Analog Converters
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9776A Datasheet, Funktion
Dual, 12-/14-/w1w6w.-DaBtaiSthe,e1t4UG.coSmPS
Digital-to-Analog Converters
AD9776A/AD9778A/AD9779A
FEATURES
Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS,
full operating conditions
Single carrier W-CDMA ACLR = 80 dBc @ 80 MHz IF
Analog output: adjustable 8.7 mA to 31.7 mA,
RL = 25 Ω to 50 Ω
Novel 2×, 4×, and 8× interpolator/coarse complex modulator
allows carrier placement anywhere in DAC bandwidth
Auxiliary DACs allow control of external VGA and offset control
Multiple chip synchronization interface
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
100-lead, exposed paddle TQFP
APPLICATIONS
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMax, GSM, LTE
Digital high or low IF synthesis
Internal digital upconversion capability
Transmit diversity
Wideband communications: LMDS/MMDS, point-to-point
GENERAL DESCRIPTION
The AD9776A/AD9778A/AD9779A are dual, 12-/14-/16-bit,
high dynamic range digital-to-analog converters (DACs) that
provide a sample rate of 1 GSPS, permitting a multicarrier
generation up to the Nyquist frequency. They include features
optimized for direct conversion transmission applications,
including complex digital modulation and gain and offset
compensation. The DAC outputs are optimized to interface
seamlessly with analog quadrature modulators such as the
ADL537x FMOD series from Analog Devices, Inc. A 3-wire
interface provides for programming/readback of many internal
parameters. Full-scale output current can be programmed over
a range of 10 mA to 30 mA. The devices are manufactured on
an advanced 0.18 μm CMOS process and operate on 1.8 V and
3.3 V supplies for a total power consumption of 1.0 W. They are
enclosed in a 100-lead thin quad flat package (TQFP).
PRODUCT HIGHLIGHTS
1. Ultralow noise and intermodulation distortion (IMD)
enable high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
2. A proprietary DAC output switching technique enhances
dynamic performance.
3. The current outputs are easily configured for various
single-ended or differential circuit topologies.
4. CMOS data input interface with adjustable setup and hold.
5. Novel 2×, 4×, and 8× interpolator/coarse complex
modulator allows carrier placement anywhere in DAC
bandwidth.
COMPLEX I AND Q
TYPICAL SIGNAL CHAIN
QUADRATURE
MODULATOR/
MIXER/
AMPLIFIER
DC
LO
DC
DIGITAL INTERPOLATION FILTERS
FPGA/ASIC/DSP
I DAC
Q DAC
POST DAC
ANALOG FILTER
A
AD9776A/AD9778A/AD9779A
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2008 Analog Devices, Inc. All rights reserved.






AD9776A Datasheet, Funktion
AD9776A/AD9778A/AD9779A
www.DataSheet4U.com
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFs = 20 mA, maximum sample rate, unless
otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input VIN Logic High
Input VIN Logic Low
Maximum Input Data Rate at Interpolation
CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37)1
Output VOUT Logic High
Output VOUT Logic Low
DATACLK Output Duty Cycle
LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−)
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH − VIDTHL
Receiver Differential Input Impedance, RIN
LVDS Input Rate
Setup Time, SYNC_I to REFCLK
Hold Time, SYNC_I to REFCLK
LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−)
Output Voltage High, VOA or VOB
Output Voltage Low, VOA or VOB
Output Differential Voltage, |VOD|
Output Offset Voltage, VOS
Output Impedance, RO
DAC CLOCK INPUT (REFCLK+, REFCLK−)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
Conditions
Min Typ Max Unit
2.0 V
0.8 V
DVDD18, CVDD18 = 1.8 V ± 5%
DVDD18, CVDD18 = 1.9 V ± 5%
DVDD18, CVDD18 = 2.0 V ± 2%
300
250
200
112.5
125
137.5
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
At 250 MHz, into 5 pF load
SYNC_I+ = VIA, SYNC_I− = VIB
Additional limits on fSYNC_I apply; see description of
Register 0x05, Bits[3:1], in Table 14
SYNC_O+ = VOA, SYNC_O− = VOB, 100 Ω termination
Single-ended
2.4 V
0.4 V
40 50 60 %
825
−100
80
20
0.4
0.55
1575
+100
120
250
mV
mV
mV
Ω
MSPS
ns
ns
1375 mV
1025
mV
150 200 250 mV
1150
1250 mV
80 100 120 Ω
DVDD18, CVDD18 = 1.8 V ± 5%, PLL off
DVDD18, CVDD18 = 1.9 V ± 5%, PLL off
DVDD18, CVDD18 = 2.0 V ± 2%, PLL off
DVDD18, CVDD18 = 2.0 V ± 2%, PLL on
400 800 2000 mV
300 400 500 mV
900 MHz
1000
MHz
1100
MHz
250 MHz
1 Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load, with maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests
using an external buffer for this signal.
Rev. B | Page 6 of 56

6 Page









AD9776A pdf, datenblatt
AD9776A/AD9778A/AD9779A
www.DataSheet4U.com
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
CVDD18 1
CVDD18 2
CGND 3
CGND 4
REFCLK+ 5
REFCLK– 6
CGND 7
CGND 8
CVDD18 9
CVDD18 10
CGND 11
AGND 12
SYNC_I+ 13
SYNC_I– 14
DGND 15
DVDD18 16
P1D13 17
P1D12 18
P1D11 19
P1D10 20
P1D9 21
DGND 22
DVDD18 23
P1D8 24
P1D7 25
PIN 1
ANALOG DOMAIN
DIGITAL DOMAIN
AD9778A
TOP VIEW
(Not to Scale)
75 I120
74 VREF
73 IPTAT
72 AGND
71 IRQ
70 RESET
69 CSB
68 SCLK
67 SDIO
66 SDO
65 PLL_LOCK
64 DGND
63 SYNC_O+
62 SYNC_O–
61 DVDD33
60 DVDD18
59 NC
58 NC
57 P2D0
56 P2D1
55 P2D2
54 DGND
53 DVDD18
52 P2D3
51 P2D4
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC = NO CONNECT
NOTES
1. FOR OPTIMAL THERMAL PERFORMANCE, THE EXPOSED
PAD SHOULD BE SOLDERED TO THE GROUND PLANE FOR
THE 100-LEAD, THERMALLY ENHANCED TQFP PACKAGE.
Figure 4. AD9778A Pin Configuration
Table 8. AD9778A Pin Function Descriptions
Pin
No. Mnemonic Description
1 CVDD18 1.8 V Clock Supply.
2 CVDD18 1.8 V Clock Supply.
3 CGND
Clock Ground.
4 CGND
Clock Common.
5 REFCLK+ Differential Clock Input.
6 REFCLK− Differential Clock Input.
7 CGND
Clock Ground.
8 CGND
Clock Ground.
9 CVDD18 1.8 V Clock Supply.
10 CVDD18 1.8 V Clock Supply.
11 CGND
Clock Ground.
12 AGND
Analog Ground.
13 SYNC_I+ Differential Synchronization Input.
14 SYNC_I− Differential Synchronization Input.
15 DGND
Digital Ground.
16 DVDD18 1.8 V Digital Supply.
17 P1D13
Port 1, Data Input D13 (MSB).
18 P1D12
Port 1, Data Input D12.
Pin
No. Mnemonic Description
19 P1D11
Port 1, Data Input D11.
20 P1D10
Port 1, Data Input D10.
21 P1D9
Port 1, Data Input D9.
22 DGND
Digital Ground.
23 DVDD18 1.8 V Digital Supply.
24 P1D8
Port 1, Data Input D8.
25 P1D7
Port 1, Data Input D7.
26 P1D6
Port 1, Data Input D6.
27 P1D5
Port 1, Data Input D5.
28 P1D4
Port 1, Data Input D4.
29 P1D3
Port 1, Data Input D3.
30 P1D2
Port 1, Data Input D2.
31 P1D1
Port 1, Data Input D1.
32 DGND
Digital Ground.
33 DVDD18 1.8 V Digital Supply.
34 P1D0
Port 1, Data Input D0 (LSB).
35 NC
No Connect.
36 NC
No Connect.
Rev. B | Page 12 of 56

12 Page





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