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PDF LT3473A Data sheet ( Hoja de datos )
| Número de pieza | LT3473A | |
| Descripción | Micropower 1A Boost Converter | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
■ Tiny Solution Size
■ Low Quiescent Current:
150µA in Active Mode (VIN = 3.6V, VOUT = 15V,
No Load)
1µA in Shutdown Mode
■ Internal 1A, 36V Switch
■ Integrated Schottky Diode
■ Integrated PNP Output Disconnect
■ Internal Reference Override Pin
■ PGOOD Pin
■ 25V at 80mA from 3.6V Input
■ Auxiliary NPNs for Intermediate
Bias Voltages (LT3473A)
■ Automatic Burst Mode® Operation at Light Load
■ Constant Switching Frequency: 1.2MHz
■ Thermal Shutdown
■ Input Range: 2.2V to 16V
■ Low Profile (3mm × 3mm) DFN Package (LT3473)
■ Low Profile (4mmU× 3mm) DFN Package (LT3473A)
APPLICATIO S
■ OLED Bias
■ CCD Bias
LT34ww7w3.Da/taLSThe3et44U7.co3mA
Micropower 1A Boost
Converter with Schottky
and Output Disconnect
DESCRIPTIO
The LT®3473/LT3473A are micropower step-up DC/DC
converters with integrated Schottky diode and output
disconnect circuitry in low profile DFN packages. The
small package size, high level of integration and the use of
tiny SMT components yield a solution size of less than
50mm2. The internal 1A switch allows the device to deliver
25V at up to 80mA from a Li-Ion cell, while automatic Burst
Mode operation maintains efficiency at light load. An
auxiliary reference input (CTRL) allows the user to over-
ride the internal 1.25V feedback reference with any lower
value, allowing full control of the output voltage during
operation. A PGOOD pin sinks current when the output
voltage reaches 90% of final value.
The LT3473A includes two NPN transistors for generating
intermediate bias voltages from the output and is offered
in a 12-lead (4mm × 3mm) DFN package. The LT3473
does not include these NPNs and is offered in an 8-lead
(3mm × 3mm) package.
The rugged 36V switch and output disconnect circuitry
allow outputs up to 34V to be easily generated in a simple
boost topology.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
VIN
3V TO 4.2V
4.7µF
6.8µH
PGOOD
OUT
CTRL
LT3473
SW
CAP
VIN
SHDN
GND
FB
VOUT
25V
2.2µF 80mA
2M
100k
0.47µF
3473 TA01a
Conversion Efficiency and Power Loss vs Output Current
80 VIN = 3.6V
VOUT = 15V
75
500
400
70 300
65 200
60 100
55
0.1
1 10
OUTPUT CURRENT (mA)
0
100
3473 TA01b
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LT34ww7w3.Da/taLSThe3et44U7.co3mA
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.
Disconnect PNP Quiescent Current
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0 5 10 15 20 25 30 35 40
CAP VOLTAGE (V)
3473 G13
SHDN Voltage to Turn-On
Disconnect PNP
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0 20 40 60 80 100
OUTPUT CURRENT (mA)
3473 G14
Auxiliary NPN VBE
1.00
0.95
0.90
0.85
IE = 1mA
0.80
0.75
0.70
0.65
IE = 100µA
0.60
0.55
0.50
– 50
0 50
TEMPERATURE (°C)
100
3473 G15
PI FU CTIO S (LT3473/LT3473A)
CAP (Pin 1/Pin 1): Internal Output Voltage. This pin is the
Schottky cathode and disconnect PNP emitter. Connect
output capacitor here.
OUT (Pin 2/Pin 2): Output of Disconnect Circuit. Bypass
this pin with capacitor to ground.
CTRL (Pin 3/Pin 8): External Reference Pin. This pin sets
the FB voltage externally between 0V and 1.25V. Tie this
pin 1.5V or higher to use the internal 1.25V reference.
FB (Pin 4/Pin 7): Feedback Pin. Pin voltage is regulated to
1.25V if internal reference is used or to the CTRL pin
voltage if the CTRL pin voltage is between 0V and 1.25V.
Connect the feedback resistor divider to this pin. The
output voltage is regulated to:
VOUT
=
VREF
•
⎛
⎝⎜
R2
R1
+
1⎞⎠⎟
PGOOD (Pin 5/Pin 9): Power Good Output. Open collector
logic output that starts to sink current when FB reaches
within 100mV of the reference voltage.
SHDN (Pin 6/Pin 10): Shutdown Pin. Connect to 1.4V or
higher to enable device; 0.2V or less to disable device. Also
functions as soft-start. Use RC filter as shown in Figure 4.
VIN (Pin 7/Pin 11): Input Supply Pin. Must be locally
bypassed with a X5R or X7R type ceramic capacitor.
SW (Pin 8/Pin 12): Switch Pin. Connect inductor here.
Minimize the metal trace area connected to the pin to
minimize EMI.
Exposed Pad (Pin 9/Pin 13): Ground. Solder directly to
PCB ground plane through multiple vias under the pack-
age for optimum thermal performance.
LT3473A Only
NB1 (Pin 3): NPN1 Base.
NE1 (Pin 4): NPN1 Emitter.
NB2 (Pin 5): NPN2 Base.
NE2 (Pin 6): NPN2 Emitter.
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LT34ww7w3.Da/taLSThe3et44U7.co3mA
PACKAGE DESCRIPTIO
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
0.675 ±0.05
R = 0.115
TYP
5
0.38 ± 0.10
8
3.5 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
PIN 1
TOP MARK
(NOTE 6)
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
0.200 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
0.00 – 0.05
4
0.25 ± 0.05
(DD8) DFN 1203
1
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
DE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708)
0.65 ±0.05
4.00 ±0.10
(2 SIDES)
R = 0.20
TYP
R = 0.115
7 TYP
0.38 ± 0.10
12
3.50 ±0.05
1.70 ±0.05
2.20 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
PIN 1
TOP MARK
(NOTE 6)
0.25 ± 0.05
0.50
BSC
3.30 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.200 REF
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
3.00 ±0.10 1.70 ± 0.10
(2 SIDES) (2 SIDES)
0.75 ±0.05
0.00 – 0.05
61
0.25 ± 0.05
0.50
BSC
3.30 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
NOTCH
(UE12/DE12) DFN 0603
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LT3473A.PDF ] | |
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