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ADP120 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP120
Beschreibung 100mA Low Quiescent Current CMOS Linear Regulator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
ADP120 Datasheet, Funktion
FEATURES
Input voltage range: 2.3 V to 5.5 V
Output voltage range: 1.2 V to 3.3 V
Output current: 100 mA
Low quiescent current
IGND = 11 μA with zero load
IGND = 22 μA with 100 mA load
Low shutdown current: <1 μA
Low dropout voltage
60 mV @ 100 mA load
High PSRR
73 dB @ 1 kHz at VOUT = 1.2 V
70 dB @ 10 kHz at VOUT = 1.2 V
Low noise: 40 μV rms at VOUT = 1.2 V
No noise bypass capacitor required
Initial accuracy: ±1%
Stable with small 1 μF ceramic output capacitor
16 fixed output voltage options
Current-limit and thermal overload protection
Logic controlled enable
5-lead TSOT package
4-ball 0.4 mm pitch WLCSP
APPLICATIONS
Mobile phones
Digital camera and audio devices
Portable and battery-powered equipment
Post regulation
GENERAL DESCRIPTION
The ADP120 is a low quiescent current, low dropout, linear
regulator that operates from 2.3 V to 5.5 V and provides up to
100 mA of output current. The low 60 mV dropout voltage at
100 mA load improves efficiency and allows operation over a
wide input voltage range. The low 25 μA of quiescent current at
full load makes the ADP120 ideal for battery-operated portable
equipment.
100 mA, Low Quiescent Current,www.DataSheet4U.com
CMOS Linear Regulator
ADP120
TYPICAL APPLICATIONS CIRCUITS
VIN = 2.3V
+
1µF
1 VIN
2 GND
VOUT 5
VOUT = 1.8V
+
1µF
3 EN
NC 4
NC = NO CONNECT
Figure 1. ADP120 TSOT with Fixed Output Voltage, 1.8 V
VIN = 2.3V
+
1µF
VIN
VOUT
VOUT = 1.8V
+
1µF
EN GND
Figure 2. ADP120 WLCSP with Fixed Output Voltage, 1.8 V
The ADP120 is available in 16 fixed output voltage options,
ranging from 1.2 V to 3.3 V. The part is optimized for stable
operation with small 1 μF ceramic output capacitors. The
ADP120 delivers good transient performance with minimal
board area.
Short-circuit protection and thermal overload protection circuits
prevent damage in adverse conditions. The ADP120 is available
in a tiny 5-lead TSOT and a 4-ball 0.4 mm pitch WLCSP for the
smallest footprint solution for use in a variety of portable
applications.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.






ADP120 Datasheet, Funktion
ADP120
www.DataSheet4U.com
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VIN 1
5 VOUT
GND 2 TOP VIEW
(Not to Scale)
EN 3
4 NC
NC = NO CONNECT
12
A VIN
VOUT
TOP VIEW
(Not to Scale)
B EN
GND
Figure 3. 5-Lead TSOT Pin Configuration
Figure 4. 4-Ball WLCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
TSOT WLCSP Mnemonic Description
1 A1 VIN
Regulator Input Supply. Bypass VIN to GND with a 1 μF or greater capacitor.
2 B2
GND
Ground.
3 B1
EN
Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic
startup, connect EN to VIN.
4 N/A NC
No Connect. Not connected internally. Not applicable (N/A) for the WLCSP.
5 A2 VOUT
Regulated Output Voltage. Bypass VOUT to GND with a 1 μF or greater capacitor.
Rev. A | Page 6 of 20

6 Page









ADP120 pdf, datenblatt
ADP120
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP120 is designed for operation with small, space-saving
ceramic capacitors, but functions with most commonly used
capacitors as long as care is taken with regard to the effective
series resistance (ESR) value. The ESR of the output capacitor
affects stability of the LDO control loop. A minimum of 0.70 μF
capacitance with an ESR of 1 Ω or less is recommended to ensure
stability of the ADP120. Transient response to changes in load
current is also affected by output capacitance. Using a larger
value of output capacitance improves the transient response of
the ADP120 to large changes in load current. Figure 28 and
Figure 29 show the transient responses for output capacitance
values of 1 μF and 4.7 μF, respectively.
ILOAD
1mA TO 100mA LOAD STEP,
2.5A/µs
VOUT
VOUT = 1.8V,
CIN = COUT = 1µF
(400ns/DIV)
Figure 28. Output Transient Response, COUT = 1 μF
ILOAD
1mA TO 100mA LOAD STEP,
2.5A/µs
VOUT
VOUT = 1.8V,
CIN = COUT = 4.7µF
(400ns/DIV)
Figure 29. Output Transient Response, COUT = 4.7 μF
Input Bypass Capacitor
Connecting a 1 μF capacitor from VIN to GND reduces the cir-
cuit sensitivity to printed circuit board (PCB) layout, especially
when long input traces or high source impedance are encountered.
If greater than 1 μF of output capacitance is required, increase
the input capacitor to match it.
www.DataSheet4U.com
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP120, as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary tempera-
ture range and dc bias conditions. X5R or X7R dielectrics with
a voltage rating of 6.3 V or 10 V are recommended for best
performance. Y5V and Z5U dielectrics are not recommended
for use with any LDO because of their poor temperature and dc
bias characteristics.
Figure 30 depicts the capacitance vs. voltage bias characteristic
of a 0402 1 μF, 10 V, X5R capacitor. The voltage stability of a capa-
citor is strongly influenced by the capacitor size and voltage rating.
In general, a capacitor in a larger package or higher voltage rating
exhibits better stability. The temperature variation of the X5R
dielectric is about ±15% over the −40°C to +85°C temperature
range and is not a function of package or voltage rating.
1.2
MURATA PART NUMBER:
GRM155R61A105KE15
1.0
0.8
0.6
0.4
0.2
0
02468
VOLTAGE (V)
Figure 30. Capacitance vs. Voltage Characteristic
10
Use Equation 1 to determine the worst-case capacitance accounting
for capacitor variation over temperature, component tolerance,
and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
(1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielec-
tric. The tolerance of the capacitor (TOL) is assumed to be 10%,
and CBIAS is 0.94 μF at 1.8 V, as shown in Figure 30.
Substituting these values in Equation 1 yields
CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
Rev. A | Page 12 of 20

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