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LC78626 Schematic ( PDF Datasheet ) - Sanyo Semicon Device

Teilenummer LC78626
Beschreibung DSP for Compact Disk Players
Hersteller Sanyo Semicon Device
Logo Sanyo Semicon Device Logo 




Gesamt 30 Seiten
LC78626 Datasheet, Funktion
Ordering number : EN5692
CMOS LSI
LC78626E
DSP for Compact Disk Players
Overview
The LC78626E is a monolithic compact disk player signal
processing and servo control CMOS IC equipped with an
internal anti-shock control function. Designed for total
functionality including support for EFM-PLL, and one-bit
D/A converter, and containing analog low-pass filter, the
LC78626E provides optimal cost-performance for low-end
CD players that provide anti-shock systems. The basic
functions provided by this IC include modulation of the
EFM signal from the optical pick-up, deinterleaving,
detection and correction of signal errors, prevention of a
maximum of approximately 10 seconds of skipping, signal
processing such as digital filtering (which is useful in
reducing the cost of the player), and processing of a
variety of servo-related commands from the
microprocessor.
Functions
• When an HF signal is input, it is sliced to precise levels
and converted to an EFM signal. The phase is compared
with the internal VCO and a PLL clock is reproduced at
an average frequency of 4.3218 MHz.
• Precise timing for a variety of required internal timing
needs (including the generation of the reference clock) is
produced by the attachment of an external 16.9344 MHz
crystal oscillator.
• The speed of revolution of the disk motor is controlled
by the frame phase difference signal generated by the
playback clock and the reference clock.
• The frame synchronizing signal is detected, stored, and
interpolated to insure stable data read back.
• The EFM signal is demodulated and converted to 8-bit
symbolic data.
• The demodulated EFM signal is divided into subcodes
and output to the external microprocessor. (Three
general I/O ports are shared [exclusively] for this
purpose.)
• After the subcode Q signal passes the CRC check, it is
output to the microprocessor through a serial
transmission (LSB first).
• The demodulated EFM signal is buffered in the internal
RAM, which is able to absorb ± 4 frame's worth of jitter
resulting from variations in the disk rotation speed.
• The demodulated EFM signal is unscrambled to a
specific sequence, and deinterleaving is performed.
• Error detection and correction is performed, as is a flag
process. (C1: two error/C2: two error correction
method.)
• The C2 flag is set after referencing the C1 flag and the
results of the C2 check, where the signal from the C2
flag is interpolated or held at its previous level. The
interpolation circuit uses double interpolation. When
there are two or more C2 flags in a row, the previous
value is held.
Continued on next page.
Package Dimensions
unit: mm
3151-QFP100E (FLP100)
[LC78626E]
SANYO: QIP100E (FLP100)
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
13098HA(OT) No. 5692-1/32






LC78626 Datasheet, Funktion
Continued from preceding page.
Parameter
Input low level current
Output high level current
Output low level current
Output off leakage current
Charge pump output current
LC78626E
Symbol
Conditions
IIL
VOH1
VOH2
VOH3
VOH4
VOH5
VOL1
VOL2
VOL3
VOL4
VOL5
IOFF1
IOFF2
IPDOH
IPDOL
DEFI, EFMI, HFL, TES, RWC, COIN, CQCK,
FMT, MR1, RES, TESE, TESD, WOK,
PAUSE IN, SHOCK, TESCLK, TESA, TESB,
TESC, TESGB, TAI, TEST1 to TEST5, CS :
VIN = 0 V
EFMO, CLV+, CLV, V/P, TOFF, TGL, JP+,
JP, PCK, FSEQ, EFLG, FSX, EMPH :
IOH = –1 mA
CONT2 to CONT5, SBSY, MUTEL, MUTER,
C2F, WRQ, SQOUT, 16M, 4.2M, EMPP,
OVF, CNTOK, NGJ : IOH = –0.5 mA
DOUT : IOH = –12 mA
OE, WE, CAS, RAS, AD9 to AD0,
DRAM3 to DRAM0 : IOH = –0.5 mA
MMC0 to MMC3 : IOH = –2 mA
EFMO, CLV+, CLV, V/P, TOFF, JP+, JP,
PCK, FSEQ, EFLG, FSX, EMPH : IOL = 1 mA
CONT2 to CONT5, SBSY, MUTEL, MUTER,
C2F, WRQ, SQOUT, 16M, 4.2M, EMPP,
OVF, CNTOK, NGJ : IOL = 2 mA
DOUT : IOL = 12 mA
OE, WE, CAS, RAS, AD9 to AD0,
DRAM3 to DRAM0 : IOL = 0.5 mA
MMC0 to MMC3 : IOL = 2 mA
PDO, CLV+, CLV, JP+, JP,
CONT2 to CONT5, DRAM0 to DRAM3,
ASRES : VOUT = VDD
PDO, CLV+, CLV, JP+, JP,
CONT2 to CONT5, DRAM0 to DRAM3,
ASRES : VOUT = 0 V
PDO : RISET = 68 k
PDO : RISET = 68 k
Ratings
min typ
–5
2.56
2.56
2.72
256
2.24
–5
30 42
–54 –42
Unit
max
µA
V
0.64
V
V
V
V
V
0.32
0.48
0.44
0.96
5
V
V
V
V
µA
µA
54 µA
–30 µA
One-bit D/A Converter Analog Characteristics at Ta = 25°C, VDD = LVDD = RVDD = 3.2 V, VSS = L/RVSS = 0 V
Parameter
Symbol
Conditions
Ratings
min typ
Total harmonic distortion rate
LCHO, RCHO; 1 kHz: Uses the 0 dB data
TRD+N input and the 20 kHz-LPF (in the AD725D).
0.015
Dynamic range
LCHO, RCHO; 1 kHz: Uses the -60 dB data
DR input, the 20 kHz-LPF (in the AD725D), and 85 90
the A filter.
Signal to noise ratio
LCHO, RCHO; 1 kHz: Uses the –0 dB data
S/N input, the 20 kHz-LPF (in the AD725D), and 87 92
the A filter.
Cross talk
LCHO, RCHO; 1 kHz: Uses the 0 dB data
CT input and the 20 kHz-LPF (in the AD725D).
79 82
Note: Measured with the normal-speed playback mode in the Sanyo one-bit D/A converter block reference digital attenuator circuit.
max
0.018
Unit
%
dB
dB
dB
Analog output
No. 5692-6/32

6 Page









LC78626 pdf, datenblatt
LC78626E
Pin Applications
1 The HF Signal Input Circuit Pin 18: EFMI, Pin 17: EFMO, Pin 1: DEFI, and Pin 20: CLV+
HF Signal
When an HF signal is input to the EFMI, an EFM signal (NRZ),
sliced at the optimal levels, is obtained.
As a countermeasure against defects, when the DEFI pin (Pin 1)
is high, the slice level control output EFMO pin (Pin 17) goes to
a high impedance state, and the slice level is held. However, this
is only enabled when the CLV is in phase-control mode, or in
other words, when the V/P pin (Pin 22) is low. This can be
structured from a combination with the DEF pin of LA9230/40
series ICs.
* When the EFMI and CLV+ signal lines are close to each other
then the error rate due to unnecessary radiation may increase.
It is recommended that these two lines be separated by a
ground line or by a VDD line as a shield line.
2 The PLL Clock Playback Circuit Pin 3: PDO, Pin 5: ISET and Pin 7: FR
Frequency
and phase
comparator
Charge pump
The VCO circuit is equipped internally, and the PLL circuit is
structured using external resistors and external capacitors. The
ISET is the reference current for the charge pump. The PDO is
the loop filter for the VCO circuit, and the FR is the resistor that
determines the frequency range of the VCO.
Reference Values
R1 = 68 kC1 = 0.1 µF (standard speed)
C1 = 0.047 µF (2× speed)
R2 = 680 C2 = 0.1 µF
R3 = 5.1 k
* It is recommended that a carbon coated resistor with a
tolerance of ± 5.0% be used for R3.
3 The VCO Monitor Pin 29: PCK
This is the monitor pin with an average frequency of 4.3218 MHz, which is a 1/2 frequency division from VCO.
4 The Sync Detect Monitor Pin 30: FSEQ
The EFM signal goes high when the frame sync signal (the true sync signal) from the PCK matches the timing (the
interpolated sync signal) generated by the counter. This serves as the sync detect monitor (holding the high level over
a single frame).
No. 5692-12/32

12 Page





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