LC78624E Schematic ( PDF Datasheet ) - Sanyo Semicon Device

Teilenummer	LC78624E
Beschreibung	Compact Disc Player DSP
Hersteller	Sanyo Semicon Device
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Gesamt 27 Seiten Ordering number : EN5811 CMOS LSI LC78624E Compact Disc Player DSP Overview The LC78624E is a CMOS LSI that implements the signal processing and servo control required by compact disc players. Including an EFM-PLL and text decoder, the LC78624E strictly limits functionality to basic signal processing and servo system operation to achieve the best cost-performance balance for low-end players. As basic functions, the LC78624E provides demodulation of the EFM signal from the optical pickup, de-interleaving, error detection and correction, and processes servo commands sent from the control microcontroller. Functions • Input signal processing: The LC78624E takes an HF signal as input, digitizes (slices) that signal at a precise level, converts that signal to an EFM signal, and generates a PLL clock with an average frequency of 4.3218 MHz by comparing the phases of that signal and an internal VCO. • Precise reference clock and necessary internal timing generation using an external 16.9344 MHz crystal oscillator • Disk motor speed control using a frame phase difference signal generated from the playback clock and the reference clock • Frame synchronization signal detection, protection and interpolation to assure stable data readout • EFM signal demodulation and conversion to 8-bit symbol data • Subcode data separation from the EFM demodulated signal and output of that data to an external microcontroller • Subcode Q signal output to a microcontroller over the serial I/O interface after performing a CRC error check (LSB first) • Serial output to a microcontroller via the text decoder of the song titles and other text data stored in the Subcode R through W channels of the read-in area • Demodulated EFM signal buffering in internal RAM to handle up to ±4 frames of disk rotational jitter • Demodulated EFM signal reordering in the prescribed order for data unscrambling and de-interleaving • Error detection, correction, and flag processing (error correction scheme: dual C1 plus dual C2 correction) • The LC78624E sets the C2 flags based on the C1 flags and a C2 check, and then performs signal interpolation or muting depending on the C2 flags. The interpolation circuit uses a dual-interpolation scheme. The previous value is held if the C2 flags indicate errors two or more times consecutively. • Support for command input from a microcontroller: commands include track jump, focus start, disk motor start/stop, muting on/off and track count (8 bit serial input) • Built-in digital output circuits. • Arbitrary track counting to support high-speed data access • Zero cross muting • Supports the implementation of a double-speed dubbing function. • Support for bilingual applications. • General-purpose I/O ports: 5 pins Features • 64 pin QFP • 5 V single-voltage power supply Package Dimensions unit: mm 3159-QFP64E [LC78624E] SANYO: QIP64E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN 20698RM (OT) No. 5811-1/27 LC78624E Figure 4 General-Purpose Port Input Timing A09897 Figure 5 General-Purpose Port Output Timing A09898 Figure 6 Text Data Output Timing A09899 No. 5811-6/27 6 Page LC78624E • CLV three-value output Code $B4 $B5 Command CLV THREE-VALUE OUTPUT CLV TWO-VALUE OUTPUT (the scheme used by previous products) The CLV three-value output command allows the CLV to be controlled by a single pin. Two-value output RES = low q Three-value output • Internal brake modes A09907 Code $C5 $C4 $A3 $CB $CA $CD $CC Command INTERNAL BRAKE ON INTERNAL BRAKE OFF INTERNAL BRAKE CONTROL INTERNAL BRAKE CONTINUOUS MODE RESET CONTINUOUS MODE TON MODE DURING INTERNAL BRAKING RESET TON MODE RES = low q q q — Issuing the internal brake-on ($C5) command sets the LC78624E to internal brake mode. In this mode, the disk deceleration state can be monitored from the WRQ pin when a brake command ($06) is executed. — In this mode the disk deceleration state is determined by counting the EFM signal density in a single frame, and when the EFM signal count falls under four, the CLV– pin is dropped to low. At the same time the WRQ signal, which functions as a brake completion monitor, goes high. When the microcontroller detects a high level on the WRQ signal, it should issue a STOP command to fully stop the disk. In internal brake continuous mode ($CB), the CLV– pin high-level output braking operation continues even after the WRQ brake completion monitor goes high. Note that if errors occur in deceleration state determination due to noise in the EFM signal, the problem may be rectified by changing the EFM signal count from four to eight with the internal brake control command ($A3). — In TOFF output disabled mode ($CD), the TOFF pin is held low during internal brake operations. We recommend using this feature, since it is effective at preventing incorrect detection at the disk mirror surface. No. 5811-12/27 12 Page
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Teilenummer	Beschreibung	Hersteller
LC78624E	Compact Disc Player DSP	Sanyo Semicon Device

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