LC78620E Schematic ( PDF Datasheet ) - Sanyo Semicon Device

Teilenummer	LC78620E
Beschreibung	Compact Disc Player DSP
Hersteller	Sanyo Semicon Device
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Gesamt 30 Seiten Ordering number : EN*5130 CMOS LSI LC78620E Compact Disc Player DSP Preliminary Overview The LC78620E is a CMOS LSI that implements the signal processing and servo control required by compact disk players, laser disks, CD-V, CD-I and related products. The LC78620E provides several types of signal processing, including demodulation of the optical pickup EFM signal, de-interleaving, error detection and correction, and digital filters that can help reduce the cost of CD player units. It also processes a rich set of servo system commands sent from the control microprocessor. It also incorporates an EFM-PLL circuit and a one-bit D/A converter. Functions • Input signal processing: The LC78620E takes an HF signal as input, digitizes (slices) that signal at a precise level, converts that signal to an EFM signal, and generates a PLL clock with an average frequency of 4.3218 MHz by comparing the phases of that signal and an internal VCO. • Precise reference clock and necessary internal timing generation using an external 16.9344 MHz crystal oscillator • Disk motor speed control using a frame phase difference signal generated from the playback clock and the reference clock • Frame synchronization signal detection, protection and interpolation to assure stable data readout • EFM signal demodulation and conversion to 8-bit symbol data • Subcode data separation from the EFM demodulated signal and output of that data to an external microprocessor • Subcode Q signal output to a microprocessor over the serial I/O interface after performing a CRC error check • Demodulated EFM signal buffering in internal RAM to handle up to ±4 frames of disk rotational jitter • Demodulated EFM signal reordering in the prescribed order for data unscrambling and de-interleaving • Error detection, correction, and flag processing (error correction scheme: dual C1 plus dual C2 correction) • The LC78620E sets the C2 flags based on the C1 flags and a C2 check, and then performs signal interpolation or muting depending on the C2 flags. The interpolation circuit uses a quadruple interpolation scheme. The output value converges to the muting level when four or more consecutive C2 flags occur. • Support for command input from a control microprocessor: commands include track jump, focus start, disk motor start/stop, muting on/off and track count (8 bit serial input) • Built-in digital output circuits. • Arbitrary track counting to support high-speed data access • Zero cross muting • D/A converter outputs with data continuity improved by 8× oversampling digital filters. (These filters function as 4× oversampling filters during double-speed playback.) • Built-in third-order ∑∆ D/A converters (PWM output) • Built-in digital attenuator (8 bits – alpha, 239 steps) • Built-in digital de-emphasis • Built-in digital level and peak meter functions • Support for bilingual applications Features • 80-pin QIP (miniature, reduced space package) • Silicon gate CMOS process (for low power) • 5 V single-voltage power supply (for use in portable products) Package Dimensions unit: mm [LC78620E] 3174-QFP80E SANYO: QIP80E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 92895HA (OT) No. 5130-1/34 LC78620E One-Bit D/A Converter Output Block Reference Circuit (normal speed playback) No. 5130-6/34 6 Page LC78620E Values in parentheses are for the LASER START #2 command. The only difference is in the FST low period. Note: 1. An FZD falling edge will not be accepted during the period that FST is low. 2. After issuing a focus start command, initialization will be performed if RWC is set high. Therefore, do not issue the next command during focus start until the focus coil drive S curve has completed. 3. When focus cannot be achieved (i.e., when FZD does not go low) the FOCS signal will remain in the high state and the lens will remain raised, so the microprocessor should initialize the system by issuing a NOTHING command. 4. When the RESET pin is set low, the LASER pin is set high directly. 5. Focus start using the DEMO pin executes a mode #1 focus start. 7. CLV servo circuit; Pin 13: CLV+, pin 14: CLV–, pin 15: V/P MSB LSB 00000100 00000101 00000110 00000111 Command DISC MOTOR START (accelerate) DISC MOTOR CLV (CLV) DISC MOTOR BRAKE (decelerate) DISC MOTOR STOP (stop) RES = low q The CLV+ pin provides the signal that accelerates the disk in the forward direction and the CLV– pin provides the signal that decelerates the disk. Commands from the control microprocessor select one of four modes; accelerate, decelerate, CLV and stop. The table below lists the CLV+ and CLV– outputs in each of these modes. Mode Accelerate Decelerate CLV Stop CLV+ High Low * Low CLV– Low High * Low No. 5130-12/34 12 Page
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